From b119241687eed6d0e0f82a24d815fd8ddf56a1de Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 14 Aug 2019 06:03:04 +0100 Subject: [PATCH] add identifying link --- simple_v_extension/abridged_spec.mdwn | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn index 0990d0d0d..8e6bbc27e 100644 --- a/simple_v_extension/abridged_spec.mdwn +++ b/simple_v_extension/abridged_spec.mdwn @@ -49,8 +49,9 @@ without requiring any special (identical, parallel variant) opcodes to do so. Associated proposals for use with 3D and HPC: -* [[sv.setvl]] - replaces the use of CSRs to set VL (saves 32 bits) -* [[mv.x]] - provides MV.swizzle and MVX (reg[rd] = reg[reg[rs]]) +* [[specification/sv.setvl]] - replaces the use of CSRs to set VL (saves + 32 bits) +* [[specification/mv.x]] - provides MV.swizzle and MVX (reg[rd] = reg[reg[rs]]) * [[ztrans_proposal]] - provides trigonometric and transcendental operations # CSRs -- 2.30.2