From b14313e45295d91b5737775ec788c76d8f0c2f93 Mon Sep 17 00:00:00 2001 From: Matt Turner Date: Mon, 6 Apr 2015 21:46:54 -0700 Subject: [PATCH] i965/fs: Manually set source regioning on PLN instructions. Like LINE (commit 92346db0), src0 must have a scalar region. Setting src1's region to <8,8,1> lets us pass a properly sized combined delta_xy argument in a few commits without getting a bogus <16,16,1> region. Reviewed-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_eu_emit.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 44b9ffb1d4e..b9faf3641cc 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -1008,7 +1008,6 @@ ALU2(DP4) ALU2(DPH) ALU2(DP3) ALU2(DP2) -ALU2(PLN) ALU3F(MAD) ALU3F(LRP) ALU1(BFREV) @@ -1112,6 +1111,19 @@ brw_LINE(struct brw_compile *p, struct brw_reg dest, return brw_alu2(p, BRW_OPCODE_LINE, dest, src0, src1); } +brw_inst * +brw_PLN(struct brw_compile *p, struct brw_reg dest, + struct brw_reg src0, struct brw_reg src1) +{ + src0.vstride = BRW_VERTICAL_STRIDE_0; + src0.width = BRW_WIDTH_1; + src0.hstride = BRW_HORIZONTAL_STRIDE_0; + src1.vstride = BRW_VERTICAL_STRIDE_8; + src1.width = BRW_WIDTH_8; + src1.hstride = BRW_HORIZONTAL_STRIDE_1; + return brw_alu2(p, BRW_OPCODE_PLN, dest, src0, src1); +} + brw_inst * brw_F32TO16(struct brw_compile *p, struct brw_reg dst, struct brw_reg src) { -- 2.30.2