From b14bc554cbfb17eaca9ffbe792f73c2535e92d61 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 16 Dec 2020 09:05:49 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64.mdwn | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index 525095124..18429fa82 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -71,6 +71,8 @@ In the following table, `` denotes the value of the corresponding register fi (**Jacob: these tables are not in the slightest bit understandable due to the use of register names that are impossible to interpret clearly**) +3 bit version + | R\*_EXTRA | Vector/Scalar
Mode | CR Register | Int/FP
Register | |-----------|------------------------|---------------|---------------------| | 000 | Scalar | `SVCR_000` | `SV[F]R_00` | @@ -82,6 +84,17 @@ In the following table, `` denotes the value of the corresponding register fi | 110 | Vector | `SVCR_100` | `SV[F]R_10` | | 111 | Vector | `SVCR_110` | `SV[F]R_11` | +2 bit version + +(**TODO, i simply cannot interpret the names, they have absolutely zero meaning to me so i have no idea how to fill in the table. this is a bad sign, indicative that the names have to go, to be replaced by something xlear snd obvious**) + +| R\*_EXTRA | Vector/Scalar
Mode | CR Register | Int/FP
Register | +|-----------|------------------------|---------------|---------------------| +| 00 | Scalar | `SVCR_000` | `SV[F]R_00` | +| 01 | Scalar | `SVCR_100` | `SV[F]R_10` | +| 10 | Vector | `SVCR_000` | `SV[F]R_00` | +| 11 | Vector | `SVCR_100` | `SV[F]R_10` | + ## ELWIDTH Encoding | Instruction Kind | ELWIDTH Value | Mnemonic | Description | -- 2.30.2