From b14e5a0ff21276be3c70b5cb9b9973e4d5df3caf Mon Sep 17 00:00:00 2001 From: whitequark Date: Mon, 31 Dec 2018 03:37:38 +0000 Subject: [PATCH] back.rtlil: fix typo. --- nmigen/back/rtlil.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index 9ad3033..10ff80f 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -557,7 +557,7 @@ class _StatementCompiler(xfrm.StatementVisitor): else: # In RTLIL, LHS and RHS of assignment must have exactly same width. rhs_sigspec = self.rhs_compiler.match_shape( - stmt.rhs, lhs_bits, rhs_sign) + stmt.rhs, lhs_bits, lhs_sign) self._case.assign(self.lhs_compiler(stmt.lhs), rhs_sigspec) def on_Switch(self, stmt): -- 2.30.2