From b157031e8a17710dd06f09418d3a5190abf1267d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 9 Mar 2015 23:29:06 +0100 Subject: [PATCH] uart/sim: add pty (optional, to use flterm) --- misoclib/com/uart/phy/sim.py | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/misoclib/com/uart/phy/sim.py b/misoclib/com/uart/phy/sim.py index c628ea92..faae3d6e 100644 --- a/misoclib/com/uart/phy/sim.py +++ b/misoclib/com/uart/phy/sim.py @@ -1,3 +1,5 @@ +import os, pty, time + from migen.fhdl.std import * from migen.flow.actor import Sink, Source @@ -15,3 +17,14 @@ class UARTPHYSim(Module): self.source.data.eq(pads.sink_data), pads.sink_ack.eq(self.source.ack) ] + + m, s = pty.openpty() + name = os.ttyname(s) + print("UART tty: "+name) + time.sleep(0.5) # pause for user + f = open("/tmp/simserial", "w") + f.write(os.ttyname(s)) + f.close() + + def do_exit(self, *args, **kwargs): + os.remove("/tmp/simserial") -- 2.30.2