From b18f7078c3e8e9a32294afe107965f28d498f759 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 27 Mar 2018 01:24:16 -0700 Subject: [PATCH] cpu: Remove ExtMachInst typedefs from the O3 CPU model. These typedefs aren't used, and they expose ISA specific types outside the ISA implementations. Change-Id: I64b9cec18d6f92765eebbdf8c8f1de15c0deba34 Reviewed-on: https://gem5-review.googlesource.com/9404 Reviewed-by: Andreas Sandberg Maintainer: Gabe Black --- src/cpu/o3/dyn_inst.hh | 2 -- src/cpu/o3/fetch.hh | 1 - 2 files changed, 3 deletions(-) diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index 8a0ae1d56..47dc830e0 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -65,8 +65,6 @@ class BaseO3DynInst : public BaseDynInst /** Binary machine instruction type. */ typedef TheISA::MachInst MachInst; - /** Extended machine instruction type. */ - typedef TheISA::ExtMachInst ExtMachInst; /** Register types. */ typedef TheISA::IntReg IntReg; typedef TheISA::FloatReg FloatReg; diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index 672fb499b..4382197f4 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -83,7 +83,6 @@ class DefaultFetch /** Typedefs from ISA. */ typedef TheISA::MachInst MachInst; - typedef TheISA::ExtMachInst ExtMachInst; class FetchTranslation : public BaseTLB::Translation { -- 2.30.2