From b1a90053f5ef590a1c200a82235f6dec46a5fd4c Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 29 Sep 2015 10:19:00 +0800 Subject: [PATCH] minor fixes --- misoc/integration/builder.py | 2 +- misoc/interconnect/wishbone2csr.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/misoc/integration/builder.py b/misoc/integration/builder.py index 0e1ed054..e0ecce6e 100644 --- a/misoc/integration/builder.py +++ b/misoc/integration/builder.py @@ -88,7 +88,7 @@ class Builder: subprocess.check_call(["make", "-C", dst_dir]) def _initialize_rom(self): - bios_file = os.path.join(self.output_dir, "software" "bios", + bios_file = os.path.join(self.output_dir, "software", "bios", "bios.bin") if self.soc.integrated_rom_size: with open(bios_file, "rb") as boot_file: diff --git a/misoc/interconnect/wishbone2csr.py b/misoc/interconnect/wishbone2csr.py index 17911abd..b065724a 100644 --- a/misoc/interconnect/wishbone2csr.py +++ b/misoc/interconnect/wishbone2csr.py @@ -1,7 +1,7 @@ from migen import * from migen.genlib.misc import timeline -from misoc.interconnect import csr, wishbone +from misoc.interconnect import csr_bus, wishbone class WB2CSR(Module): @@ -10,7 +10,7 @@ class WB2CSR(Module): bus_wishbone = wishbone.Interface() self.wishbone = bus_wishbone if bus_csr is None: - bus_csr = csr.Interface() + bus_csr = csr_bus.Interface() self.csr = bus_csr ### -- 2.30.2