From b1ad9bcdb2090909914d6ce5eed5114745147d0a Mon Sep 17 00:00:00 2001 From: Sandipan Das Date: Sat, 6 Feb 2021 17:22:23 +0530 Subject: [PATCH] arch-power: Add move condition field instructions This adds the following instructions. * Move to CR from XER Extended (mcrxrx) * Move To One Condition Register Field (mtocrf) * Move From One Condition Register Field (mfocrf) Change-Id: I5014160d77b1b759c1cb8cba34e6dd20eb2b5205 Signed-off-by: Sandipan Das --- src/arch/power/isa/decoder.isa | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa index 7f79d3c88..4ecee98cd 100644 --- a/src/arch/power/isa/decoder.isa +++ b/src/arch/power/isa/decoder.isa @@ -720,6 +720,16 @@ decode PO default Unknown::unknown() { 68: td({{ Ra }}, {{ Rb }}); } + format IntOp { + 576: mcrxrx({{ + uint8_t res; + Xer xer = XER; + res = (xer.ov << 3) | (xer.ov32 << 2) | + (xer.ca << 1) | xer.ca32; + CR = insertCRField(CR, BF, res); + }}); + } + format StoreIndexOp { 663: stfsx({{ Mem_sf = Fs_sf; }}); 727: stfdx({{ Mem_df = Fs; }}); @@ -982,10 +992,26 @@ decode PO default Unknown::unknown() { } CR = (Rs & mask) | (CR & ~mask); }}); + + 1: mtocrf({{ + int count = popCount(FXM); + uint32_t mask = 0xf << (4 * findMsbSet(FXM)); + if (count == 1) { + CR = (Rs & mask) | (CR & ~mask); + } + }}); } 19: decode S { 0: mfcr({{ Rt = CR; }}); + + 1: mfocrf({{ + int count = popCount(FXM); + uint64_t mask = 0xf << (4 * findMsbSet(FXM)); + if (count == 1) { + Rt = CR & mask; + } + }}); } 512: mcrxr({{ -- 2.30.2