From b1b49824a8037a79e6a819bdd072820038f77586 Mon Sep 17 00:00:00 2001 From: Michael Collison Date: Wed, 25 Nov 2015 06:51:55 +0000 Subject: [PATCH] 2015-11-24 Michael Collison * config/aarch64/aarch64-simd.md (widen_ssum, widen_usum) (aarch64_w_internal): New patterns * config/aarch64/iterators.md (Vhalf, VDBLW): New mode attributes. * gcc.target/aarch64/saddw-1.c: New test. * gcc.target/aarch64/saddw-2.c: New test. * gcc.target/aarch64/uaddw-1.c: New test. * gcc.target/aarch64/uaddw-2.c: New test. * gcc.target/aarch64/uaddw-3.c: New test. * lib/target-support.exp (check_effective_target_vect_widen_sum_hi_to_si_pattern): Add aarch64 to list of support targets. From-SVN: r230853 --- gcc/ChangeLog | 6 ++ gcc/config/aarch64/aarch64-simd.md | 68 ++++++++++++++++++++++ gcc/config/aarch64/iterators.md | 12 ++++ gcc/testsuite/ChangeLog | 11 ++++ gcc/testsuite/gcc.target/aarch64/saddw-1.c | 16 +++++ gcc/testsuite/gcc.target/aarch64/saddw-2.c | 16 +++++ gcc/testsuite/gcc.target/aarch64/uaddw-1.c | 16 +++++ gcc/testsuite/gcc.target/aarch64/uaddw-2.c | 17 ++++++ gcc/testsuite/gcc.target/aarch64/uaddw-3.c | 16 +++++ gcc/testsuite/lib/target-supports.exp | 1 + 10 files changed, 179 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/saddw-1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/saddw-2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/uaddw-1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/uaddw-2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/uaddw-3.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 30ff440cd05..fd78249b010 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2015-11-24 Michael Collison + + * config/aarch64/aarch64-simd.md (widen_ssum, widen_usum) + (aarch64_w_internal): New patterns + * config/aarch64/iterators.md (Vhalf, VDBLW): New mode attributes. + 2015-11-24 Steve Ellcey * frame-header-opt.c (gate): Check for optimize > 0. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 3fa23b30293..79be6beec49 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -2777,6 +2777,62 @@ ;; w. +(define_expand "widen_ssum3" + [(set (match_operand: 0 "register_operand" "") + (plus: (sign_extend: + (match_operand:VQW 1 "register_operand" "")) + (match_operand: 2 "register_operand" "")))] + "TARGET_SIMD" + { + rtx p = aarch64_simd_vect_par_cnst_half (mode, false); + rtx temp = gen_reg_rtx (GET_MODE (operands[0])); + + emit_insn (gen_aarch64_saddw_internal (temp, operands[2], + operands[1], p)); + emit_insn (gen_aarch64_saddw2 (operands[0], temp, operands[1])); + DONE; + } +) + +(define_expand "widen_ssum3" + [(set (match_operand: 0 "register_operand" "") + (plus: (sign_extend: + (match_operand:VD_BHSI 1 "register_operand" "")) + (match_operand: 2 "register_operand" "")))] + "TARGET_SIMD" +{ + emit_insn (gen_aarch64_saddw (operands[0], operands[2], operands[1])); + DONE; +}) + +(define_expand "widen_usum3" + [(set (match_operand: 0 "register_operand" "") + (plus: (zero_extend: + (match_operand:VQW 1 "register_operand" "")) + (match_operand: 2 "register_operand" "")))] + "TARGET_SIMD" + { + rtx p = aarch64_simd_vect_par_cnst_half (mode, false); + rtx temp = gen_reg_rtx (GET_MODE (operands[0])); + + emit_insn (gen_aarch64_uaddw_internal (temp, operands[2], + operands[1], p)); + emit_insn (gen_aarch64_uaddw2 (operands[0], temp, operands[1])); + DONE; + } +) + +(define_expand "widen_usum3" + [(set (match_operand: 0 "register_operand" "") + (plus: (zero_extend: + (match_operand:VD_BHSI 1 "register_operand" "")) + (match_operand: 2 "register_operand" "")))] + "TARGET_SIMD" +{ + emit_insn (gen_aarch64_uaddw (operands[0], operands[2], operands[1])); + DONE; +}) + (define_insn "aarch64_w" [(set (match_operand: 0 "register_operand" "=w") (ADDSUB: (match_operand: 1 "register_operand" "w") @@ -2787,6 +2843,18 @@ [(set_attr "type" "neon__widen")] ) +(define_insn "aarch64_w_internal" + [(set (match_operand: 0 "register_operand" "=w") + (ADDSUB: (match_operand: 1 "register_operand" "w") + (ANY_EXTEND: + (vec_select: + (match_operand:VQW 2 "register_operand" "w") + (match_operand:VQW 3 "vect_par_cnst_lo_half" "")))))] + "TARGET_SIMD" + "w\\t%0., %1., %2." + [(set_attr "type" "neon__widen")] +) + (define_insn "aarch64_w2_internal" [(set (match_operand: 0 "register_operand" "=w") (ADDSUB: (match_operand: 1 "register_operand" "w") diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 422bc879f7f..d6a57f68b80 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -479,6 +479,13 @@ (V4SF "V2SF") (V4HF "V2HF") (V8HF "V4HF") (V2DF "DF")]) +;; Half modes of all vector modes, in lower-case. +(define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi") + (V4HI "v2hi") (V8HI "v4hi") + (V2SI "si") (V4SI "v2si") + (V2DI "di") (V2SF "sf") + (V4SF "v2sf") (V2DF "df")]) + ;; Double modes of vector modes. (define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI") (V4HF "V8HF") @@ -496,6 +503,11 @@ (SI "v2si") (DI "v2di") (DF "v2df")]) +;; Modes with double-width elements. +(define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI") + (V4HI "V2SI") (V8HI "V4SI") + (V2SI "DI") (V4SI "V2DI")]) + ;; Narrowed modes for VDN. (define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI") (DI "V2SI")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5b240482457..cff124d30a0 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,14 @@ +2015-11-24 Michael Collison + + * gcc.target/aarch64/saddw-1.c: New test. + * gcc.target/aarch64/saddw-2.c: New test. + * gcc.target/aarch64/uaddw-1.c: New test. + * gcc.target/aarch64/uaddw-2.c: New test. + * gcc.target/aarch64/uaddw-3.c: New test. + * lib/target-support.exp + (check_effective_target_vect_widen_sum_hi_to_si_pattern): + Add aarch64 to list of support targets. + 2015-11-24 Steve Ellcey * gcc.target/mips/frame-header-4.c: New test. diff --git a/gcc/testsuite/gcc.target/aarch64/saddw-1.c b/gcc/testsuite/gcc.target/aarch64/saddw-1.c new file mode 100644 index 00000000000..7500fb82444 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/saddw-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +int +t6(int len, void * dummy, short * __restrict x) +{ + len = len & ~31; + int result = 0; + __asm volatile (""); + for (int i = 0; i < len; i++) + result += x[i]; + return result; +} + +/* { dg-final { scan-assembler "saddw" } } */ +/* { dg-final { scan-assembler "saddw2" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/saddw-2.c b/gcc/testsuite/gcc.target/aarch64/saddw-2.c new file mode 100644 index 00000000000..5d9c8d9edc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/saddw-2.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +int +t6(int len, void * dummy, int * __restrict x) +{ + len = len & ~31; + long long result = 0; + __asm volatile (""); + for (int i = 0; i < len; i++) + result += x[i]; + return result; +} + +/* { dg-final { scan-assembler "saddw" } } */ +/* { dg-final { scan-assembler "saddw2" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/uaddw-1.c b/gcc/testsuite/gcc.target/aarch64/uaddw-1.c new file mode 100644 index 00000000000..3d55ecfdb32 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/uaddw-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +int +t6(int len, void * dummy, unsigned short * __restrict x) +{ + len = len & ~31; + unsigned int result = 0; + __asm volatile (""); + for (int i = 0; i < len; i++) + result += x[i]; + return result; +} + +/* { dg-final { scan-assembler "uaddw" } } */ +/* { dg-final { scan-assembler "uaddw2" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/uaddw-2.c b/gcc/testsuite/gcc.target/aarch64/uaddw-2.c new file mode 100644 index 00000000000..fd3b578c0bb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/uaddw-2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +int +t6(int len, void * dummy, unsigned short * __restrict x) +{ + len = len & ~31; + unsigned int result = 0; + __asm volatile (""); + for (int i = 0; i < len; i++) + result += x[i]; + return result; +} + +/* { dg-final { scan-assembler "uaddw" } } */ +/* { dg-final { scan-assembler "uaddw2" } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/uaddw-3.c b/gcc/testsuite/gcc.target/aarch64/uaddw-3.c new file mode 100644 index 00000000000..499af511521 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/uaddw-3.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +int +t6(int len, void * dummy, char * __restrict x) +{ + len = len & ~31; + unsigned short result = 0; + __asm volatile (""); + for (int i = 0; i < len; i++) + result += x[i]; + return result; +} + +/* { dg-final { scan-assembler "uaddw" } } */ +/* { dg-final { scan-assembler "uaddw2" } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 3eb46f21083..254c4e3cac3 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -4163,6 +4163,7 @@ proc check_effective_target_vect_widen_sum_hi_to_si_pattern { } { } else { set et_vect_widen_sum_hi_to_si_pattern_saved 0 if { [istarget powerpc*-*-*] + || [istarget aarch64*-*-*] || [istarget ia64-*-*] } { set et_vect_widen_sum_hi_to_si_pattern_saved 1 } -- 2.30.2