From b1c9ed25a55363f8d78eb952f8bd28160ed3453e Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Wed, 30 Aug 2017 09:38:34 +0100 Subject: [PATCH] i965: drop brw->has_surface_tile_offset in favor of devinfo's MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Lionel Landwerlin Reviewed-by: Samuel Iglesias Gonsálvez Reviewed-by: Emil Velikov --- src/mesa/drivers/dri/i965/brw_context.c | 1 - src/mesa/drivers/dri/i965/brw_context.h | 1 - src/mesa/drivers/dri/i965/brw_misc_state.c | 3 ++- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 9 +++++---- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 ++- 5 files changed, 9 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 41f56f1d525..730e9d82e55 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -860,7 +860,6 @@ brwCreateContext(gl_api api, brw->has_hiz = devinfo->has_hiz_and_separate_stencil; brw->has_separate_stencil = devinfo->has_hiz_and_separate_stencil; - brw->has_surface_tile_offset = devinfo->has_surface_tile_offset; brw->needs_unlit_centroid_workaround = devinfo->needs_unlit_centroid_workaround; diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index d6fb9146129..0c2e02a7159 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -749,7 +749,6 @@ struct brw_context bool has_hiz; bool has_separate_stencil; bool has_swizzling; - bool has_surface_tile_offset; /** * Some versions of Gen hardware don't do centroid interpolation correctly diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index bd36fa39c4d..9b8ae70f103 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -136,6 +136,7 @@ static bool rebase_depth_stencil(struct brw_context *brw, struct intel_renderbuffer *irb, bool invalidate) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_context *ctx = &brw->ctx; uint32_t tile_mask_x = 0, tile_mask_y = 0; @@ -156,7 +157,7 @@ rebase_depth_stencil(struct brw_context *brw, struct intel_renderbuffer *irb, bool rebase = tile_x & 7 || tile_y & 7; /* We didn't even have intra-tile offsets before g45. */ - rebase |= (!brw->has_surface_tile_offset && (tile_x || tile_y)); + rebase |= (!devinfo->has_surface_tile_offset && (tile_x || tile_y)); if (rebase) { perf_debug("HW workaround: blitting depth level %d to a temporary " diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index f9628e928a4..1f89b723544 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -77,8 +77,9 @@ get_isl_surf(struct brw_context *brw, struct intel_mipmap_tree *mt, { *surf = mt->surf; + const struct gen_device_info *devinfo = &brw->screen->devinfo; const enum isl_dim_layout dim_layout = - get_isl_dim_layout(&brw->screen->devinfo, mt->surf.tiling, target); + get_isl_dim_layout(devinfo, mt->surf.tiling, target); if (surf->dim_layout == dim_layout) return; @@ -92,7 +93,7 @@ get_isl_surf(struct brw_context *brw, struct intel_mipmap_tree *mt, * texel of the level instead of relying on the usual base level/layer * controls. */ - assert(brw->has_surface_tile_offset); + assert(devinfo->has_surface_tile_offset); assert(view->levels == 1 && view->array_len == 1); assert(*tile_x == 0 && *tile_y == 0); @@ -910,7 +911,7 @@ gen4_update_renderbuffer_surface(struct brw_context *brw, mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb)); /* BRW_NEW_FS_PROG_DATA */ - if (rb->TexImage && !brw->has_surface_tile_offset) { + if (rb->TexImage && !devinfo->has_surface_tile_offset) { intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y); if (tile_x != 0 || tile_y != 0) { @@ -954,7 +955,7 @@ gen4_update_renderbuffer_surface(struct brw_context *brw, surf[4] = brw_get_surface_num_multisamples(mt->surf.samples); - assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0)); + assert(devinfo->has_surface_tile_offset || (tile_x == 0 && tile_y == 0)); /* Note that the low bits of these fields are missing, so * there's the possibility of getting in trouble. */ diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 75f206a9800..79afdc5342b 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -1043,7 +1043,8 @@ intel_miptree_create_for_dri_image(struct brw_context *brw, * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has * trouble resolving back to destination image due to alignment issues. */ - if (!brw->has_surface_tile_offset) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + if (!devinfo->has_surface_tile_offset) { uint32_t draw_x, draw_y; intel_miptree_get_tile_offsets(mt, 0, 0, &draw_x, &draw_y); -- 2.30.2