From b211c5958a31f1deada10926f384d999043f0a8a Mon Sep 17 00:00:00 2001 From: Will Schmidt Date: Fri, 26 Jan 2018 15:37:34 +0000 Subject: [PATCH] fold-vec-abs-int.c: Remove scan-assembler stanzas. [testsuite] 2018-01-26 Will Schmidt * gcc.target/powerpc/fold-vec-abs-int.c: Remove scan-assembler stanzas. * gcc.target/powerpc/fold-vec-abs-int-fwrap.c: Same. * gcc.target/powerpc/fold-vec-abs-int.p7.c: New. * gcc.target/powerpc/fold-vec-abs-int.p8.c: New. * gcc.target/powerpc/fold-vec-abs-int.p9.c: New. * gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c: New. * gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c: New. * gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c: New. * gcc.target/powerpc/fold-vec-abs-longlong.c: Remove scan-assembler stanzas. * gcc.target/powerpc/fold-vec-abs-longlong-fwrap.c: Same. * gcc.target/powerpc/fold-vec-abs-longlong.p7.c: New. * gcc.target/powerpc/fold-vec-abs-longlong.p8.c: New. * gcc.target/powerpc/fold-vec-abs-longlong.p9.c: New. * gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p7.c: New. * gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c: New. * gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c: New. * gcc.target/powerpc/fold-vec-abs-short.c: Add xxspltib to valid instruction list. * gcc.target/powerpc/fold-vec-abs-short-fwrapv.c: Same. From-SVN: r257097 --- gcc/testsuite/ChangeLog | 23 +++++++++++++++++++ .../powerpc/fold-vec-abs-int-fwrapv.c | 4 +--- .../powerpc/fold-vec-abs-int-fwrapv.p7.c | 20 ++++++++++++++++ .../powerpc/fold-vec-abs-int-fwrapv.p8.c | 20 ++++++++++++++++ .../powerpc/fold-vec-abs-int-fwrapv.p9.c | 19 +++++++++++++++ .../gcc.target/powerpc/fold-vec-abs-int.c | 4 +--- .../gcc.target/powerpc/fold-vec-abs-int.p7.c | 19 +++++++++++++++ .../gcc.target/powerpc/fold-vec-abs-int.p8.c | 20 ++++++++++++++++ .../gcc.target/powerpc/fold-vec-abs-int.p9.c | 18 +++++++++++++++ .../powerpc/fold-vec-abs-longlong-fwrapv.c | 5 ++-- .../powerpc/fold-vec-abs-longlong-fwrapv.p8.c | 20 ++++++++++++++++ .../powerpc/fold-vec-abs-longlong-fwrapv.p9.c | 18 +++++++++++++++ .../powerpc/fold-vec-abs-longlong.c | 4 +--- .../powerpc/fold-vec-abs-longlong.p8.c | 18 +++++++++++++++ .../powerpc/fold-vec-abs-longlong.p9.c | 17 ++++++++++++++ 15 files changed, 217 insertions(+), 12 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p7.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p8.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p9.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p8.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p9.c diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index fa0a167e2fd..adf8c01a82e 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,26 @@ +2018-01-26 Will Schmidt + + * gcc.target/powerpc/fold-vec-abs-int.c: Remove scan-assembler stanzas. + * gcc.target/powerpc/fold-vec-abs-int-fwrap.c: Same. + * gcc.target/powerpc/fold-vec-abs-int.p7.c: New. + * gcc.target/powerpc/fold-vec-abs-int.p8.c: New. + * gcc.target/powerpc/fold-vec-abs-int.p9.c: New. + * gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c: New. + * gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c: New. + * gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c: New. + * gcc.target/powerpc/fold-vec-abs-longlong.c: Remove scan-assembler + stanzas. + * gcc.target/powerpc/fold-vec-abs-longlong-fwrap.c: Same. + * gcc.target/powerpc/fold-vec-abs-longlong.p7.c: New. + * gcc.target/powerpc/fold-vec-abs-longlong.p8.c: New. + * gcc.target/powerpc/fold-vec-abs-longlong.p9.c: New. + * gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p7.c: New. + * gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c: New. + * gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c: New. + * gcc.target/powerpc/fold-vec-abs-short.c: Add xxspltib to valid + instruction list. + * gcc.target/powerpc/fold-vec-abs-short-fwrapv.c: Same. + 2018-01-26 Will Schmidt * gcc.target/powerpc/fold-vec-cmp-int.c: Delete. diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c index 34dead4e916..22eec38f25e 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c @@ -13,6 +13,4 @@ test1 (vector signed int x) return vec_abs (x); } -/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */ -/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */ -/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */ +/* scan-assembler stanzas moved to fold-vec-abs-int-fwrapv.p*.c tests. */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c new file mode 100644 index 00000000000..739f1c97df8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c @@ -0,0 +1,20 @@ +/* Verify that overloaded built-ins for vec_abs with int + inputs produce the right results when -mcpu=power7 is specified. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2 -mcpu=power7 -fwrapv" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ + +#include + +vector signed int +test1 (vector signed int x) +{ + return vec_abs (x); +} + +/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */ +/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c new file mode 100644 index 00000000000..8c284ff35b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c @@ -0,0 +1,20 @@ +/* Verify that overloaded built-ins for vec_abs with int + inputs produce the right results when -mcpu=power8 is specified. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2 -mcpu=power8 -fwrapv" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ + +#include + +vector signed int +test1 (vector signed int x) +{ + return vec_abs (x); +} + +/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */ +/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c new file mode 100644 index 00000000000..cde86b8cacd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c @@ -0,0 +1,19 @@ +/* Verify that overloaded built-ins for vec_abs with int + inputs produce the right results when -mcpu=power9 is specified. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2 -mcpu=power9 -fwrapv" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ + +#include + +vector signed int +test1 (vector signed int x) +{ + return vec_abs (x); +} + +/* { dg-final { scan-assembler-times "vnegw" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c index 77d9ca5c26b..4fb3fbe8664 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c @@ -13,6 +13,4 @@ test1 (vector signed int x) return vec_abs (x); } -/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */ -/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */ -/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */ +/* scan-assembler entries moved to fold-vec-abs-int.p*.c files. */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p7.c new file mode 100644 index 00000000000..81b0fc0a5a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p7.c @@ -0,0 +1,19 @@ +/* Verify that overloaded built-ins for vec_abs with int + inputs produce the right code when -mcpu=power7 is specified. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2 -mcpu=power7" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ + +#include + +vector signed int +test1 (vector signed int x) +{ + return vec_abs (x); +} + +/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */ +/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p8.c new file mode 100644 index 00000000000..4e55e0eff22 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p8.c @@ -0,0 +1,20 @@ +/* Verify that overloaded built-ins for vec_abs with int + inputs produce the right code when -mcpu=power8 is specified. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2 -mcpu=power8" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ + +#include + +vector signed int +test1 (vector signed int x) +{ + return vec_abs (x); +} + +/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */ +/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p9.c new file mode 100644 index 00000000000..6f2c686999b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p9.c @@ -0,0 +1,18 @@ +/* Verify that overloaded built-ins for vec_abs with int + inputs produce the right code when -mcpu=power9 is specified. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2 -mcpu=power9" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ + +#include + +vector signed int +test1 (vector signed int x) +{ + return vec_abs (x); +} + +/* { dg-final { scan-assembler-times "vnegw" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c index 934618b91b2..6c3108c60c7 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c @@ -13,6 +13,5 @@ test3 (vector signed long long x) return vec_abs (x); } -/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */ -/* { dg-final { scan-assembler-times "vsubudm" 1 } } */ -/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */ +/* scan-assembler stanzas moved to fold-vec-abs-longlong.p*.c. */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c new file mode 100644 index 00000000000..244c247efba --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c @@ -0,0 +1,20 @@ + +/* Verify that overloaded built-ins for vec_abs with long long + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -O2 -mcpu=power8" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ + +#include + +vector signed long long +test3 (vector signed long long x) +{ + return vec_abs (x); +} + +/* { dg-final { scan-assembler-times "vspltisw" 1 } } */ +/* { dg-final { scan-assembler-times "vsubudm" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c new file mode 100644 index 00000000000..8f1545d17c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c @@ -0,0 +1,18 @@ +/* Verify that overloaded built-ins for vec_abs with long long + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mpower9-vector -O2 -mcpu=power9" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ + +#include + +vector signed long long +test3 (vector signed long long x) +{ + return vec_abs (x); +} + +/* { dg-final { scan-assembler-times "vnegd" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c index 5b59d19346d..4f5148ed237 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c @@ -13,6 +13,4 @@ test3 (vector signed long long x) return vec_abs (x); } -/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */ -/* { dg-final { scan-assembler-times "vsubudm" 1 } } */ -/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */ +/* scan-assembler stanzas moved to fold-vec-abs-longlong.p*.c . */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p8.c new file mode 100644 index 00000000000..4fa0b6db316 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p8.c @@ -0,0 +1,18 @@ +/* Verify that overloaded built-ins for vec_abs with long long + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -O2 -mcpu=power8" } */ + +#include + +vector signed long long +test3 (vector signed long long x) +{ + return vec_abs (x); +} + +/* { dg-final { scan-assembler-times "vspltisw" 1 } } */ +/* { dg-final { scan-assembler-times "vsubudm" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p9.c new file mode 100644 index 00000000000..16906ed9007 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p9.c @@ -0,0 +1,17 @@ +/* Verify that overloaded built-ins for vec_abs with long long + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mpower9-vector -O2 -mcpu=power9" } */ + +#include + +vector signed long long +test3 (vector signed long long x) +{ + return vec_abs (x); +} + +/* { dg-final { scan-assembler-times "vnegd" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */ -- 2.30.2