From b21ebe1859df2f9bd1791de34633a85918651c13 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 26 Jul 2014 17:22:18 +0200
Subject: [PATCH] Added tests/various/submod_extract.ys

---
 Makefile                        |  1 +
 tests/various/run-test.sh       |  6 ++++++
 tests/various/submod_extract.ys | 21 +++++++++++++++++++++
 3 files changed, 28 insertions(+)
 create mode 100755 tests/various/run-test.sh
 create mode 100644 tests/various/submod_extract.ys

diff --git a/Makefile b/Makefile
index b87a7474e..6809ffd01 100644
--- a/Makefile
+++ b/Makefile
@@ -225,6 +225,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
 	cd tests/share && bash run-test.sh
 	cd tests/techmap && bash run-test.sh
 	cd tests/memories && bash run-test.sh
+	cd tests/various && bash run-test.sh
 	cd tests/sat && bash run-test.sh
 	@echo ""
 	@echo "  Passed \"make test\"."
diff --git a/tests/various/run-test.sh b/tests/various/run-test.sh
new file mode 100755
index 000000000..67e1beb23
--- /dev/null
+++ b/tests/various/run-test.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+set -e
+for x in *.ys; do
+	echo "Running $x.."
+	../../yosys -ql ${x%.ys}.log $x
+done
diff --git a/tests/various/submod_extract.ys b/tests/various/submod_extract.ys
new file mode 100644
index 000000000..8d11c21d3
--- /dev/null
+++ b/tests/various/submod_extract.ys
@@ -0,0 +1,21 @@
+read_verilog << EOT
+  module test(input [7:0] a, b, c, d, output [7:0] x, y, z);
+    assign x = a + b, y = b + c, z = c + d;
+  endmodule
+EOT
+
+copy test gold
+rename test gate
+
+submod -name mycell gate/x %ci*
+design -copy-to mymap mycell
+extract -map %mymap gate
+
+select -assert-count 3 gold/t:*
+select -assert-count 3 gold/t:$add
+
+select -assert-count 3 gate/t:*
+select -assert-count 3 gate/t:mycell
+
+miter -equiv -flatten gold gate miter
+sat -verify -prove trigger 0 miter
-- 
2.30.2