From b2250970b4cd4928ba02f4e6e47d22d01f9413ad Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Tue, 21 Jun 2022 23:58:29 +0100
Subject: [PATCH]

---
 openpower/sv/vector_ops.mdwn | 1 +
 1 file changed, 1 insertion(+)

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 97bf4d4c3..cd6d492ef 100644
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -12,6 +12,7 @@ Links:
  out of scope for this document [[openpower/sv/3d_vector_ops]]
 * [[simple_v_extension/specification/bitmanip]] previous version,
   contains pseudocode for sof, sif, sbf
+* https://en.m.wikipedia.org/wiki/X86_Bit_manipulation_instruction_set#TBM_(Trailing_Bit_Manipulation)
 
 The core Power ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism.
 Therefore there are not that many cases where *actual* Vector
-- 
2.30.2