From b23801eceac0f70ee681026fc333c1c8ee1a4781 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 6 Jul 2022 08:12:06 +0100 Subject: [PATCH] converted test_caller_svstate.py to new reg format https://bugs.libre-soc.org/show_bug.cgi?id=884#c0 --- .../decoder/isa/test_caller_svstate.py | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/openpower/decoder/isa/test_caller_svstate.py b/src/openpower/decoder/isa/test_caller_svstate.py index e228b8ce..5ba0f77f 100644 --- a/src/openpower/decoder/isa/test_caller_svstate.py +++ b/src/openpower/decoder/isa/test_caller_svstate.py @@ -35,7 +35,7 @@ class SVSTATETestCase(FHDLTestCase): because whilst the Vector instruction was moved on by srcstep, the Scalar one is NOT moved on. """ - isa = SVP64Asm(['sv.add 1, 5.v, 9.v' + isa = SVP64Asm(['sv.add 1, *5, *9' ]) lst = list(isa) print ("listing", lst) @@ -66,11 +66,11 @@ class SVSTATETestCase(FHDLTestCase): def test_svstep_add_1(self): """tests svstep with an add, using scalar adds, when it reaches VL lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1", - 'sv.add 1, 5.v, 9.v', - 'sv.addi 12.v, 1, 1', + 'sv.add 1, *5, *9', + 'sv.addi *12, 1, 1', "setvl. 0, 0, 1, 1, 0, 0", - 'sv.add 1, 5.v, 9.v', - 'sv.addi 12.v, 1, 1', + 'sv.add 1, *5, *9', + 'sv.addi *12, 1, 1', "setvl. 0, 0, 1, 1, 0, 0" ]) @@ -98,11 +98,11 @@ class SVSTATETestCase(FHDLTestCase): """ lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1", - 'sv.add 1, 5.v, 9.v', # scalar dest (into r1) - 'sv.addi 12.v, 1, 1', # scalar src (from r1) + 'sv.add 1, *5, *9', # scalar dest (into r1) + 'sv.addi *12, 1, 1', # scalar src (from r1) "setvl. 0, 0, 1, 1, 0, 0", # svstep - 'sv.add 1, 5.v, 9.v', # again, scalar dest - 'sv.addi 12.v, 1, 1', # but vector dest + 'sv.add 1, *5, *9', # again, scalar dest + 'sv.addi *12, 1, 1', # but vector dest "setvl. 0, 0, 1, 1, 0, 0" # svstep (end: sets CR0.SO) ]) lst = list(lst) -- 2.30.2