From b24a46beddca2278e1879b1ed5086bfd957eebb7 Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Thu, 16 Aug 2018 21:44:38 +0200 Subject: [PATCH] rs6000: Remove "length 4" from other insns There were many insns that set "length 4" explicitly while that does not make anything clearer to the reader. So, simplify the code. * config/rs6000/altivec.md: Don't set length attribute to the default value. * config/rs6000/darwin.md: Ditto. * config/rs6000/dfp.md: Ditto. * config/rs6000/htm.md: Ditto. * config/rs6000/rs6000.md: Ditto. * config/rs6000/sync.md: Ditto. * config/rs6000/vsx.md: Ditto. From-SVN: r263603 --- gcc/ChangeLog | 11 ++++++ gcc/config/rs6000/altivec.md | 66 ++++++++++++------------------------ gcc/config/rs6000/darwin.md | 33 ++++++------------ gcc/config/rs6000/dfp.md | 6 ++-- gcc/config/rs6000/htm.md | 36 +++++++------------- gcc/config/rs6000/rs6000.md | 57 +++++++++++-------------------- gcc/config/rs6000/sync.md | 6 ++-- gcc/config/rs6000/vsx.md | 3 +- 8 files changed, 80 insertions(+), 138 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 19f675d3071..cf134ccdd50 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2018-08-16 Segher Boessenkool + + * config/rs6000/altivec.md: Don't set length attribute to the default + value. + * config/rs6000/darwin.md: Ditto. + * config/rs6000/dfp.md: Ditto. + * config/rs6000/htm.md: Ditto. + * config/rs6000/rs6000.md: Ditto. + * config/rs6000/sync.md: Ditto. + * config/rs6000/vsx.md: Ditto. + 2018-08-16 Segher Boessenkool * config/rs6000/altivec.md: Don't set length attribute to the default diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 1af96877424..3419e3a7a1c 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2042,8 +2042,7 @@ "@ vperm %0,%1,%2,%3 xxperm %x0,%x1,%x3" - [(set_attr "type" "vecperm") - (set_attr "length" "4")]) + [(set_attr "type" "vecperm")]) (define_insn "altivec_vperm_v8hiv16qi" [(set (match_operand:V16QI 0 "register_operand" "=v,?wo") @@ -2055,8 +2054,7 @@ "@ vperm %0,%1,%2,%3 xxperm %x0,%x1,%x3" - [(set_attr "type" "vecperm") - (set_attr "length" "4")]) + [(set_attr "type" "vecperm")]) (define_expand "altivec_vperm__uns" [(set (match_operand:VM 0 "register_operand") @@ -2083,8 +2081,7 @@ "@ vperm %0,%1,%2,%3 xxperm %x0,%x1,%x3" - [(set_attr "type" "vecperm") - (set_attr "length" "4")]) + [(set_attr "type" "vecperm")]) (define_expand "vec_permv16qi" [(set (match_operand:V16QI 0 "register_operand") @@ -2110,8 +2107,7 @@ "@ vpermr %0,%1,%2,%3 xxpermr %x0,%x1,%x3" - [(set_attr "type" "vecperm") - (set_attr "length" "4")]) + [(set_attr "type" "vecperm")]) (define_insn "altivec_vrfip" ; ceil [(set (match_operand:V4SF 0 "register_operand" "=v") @@ -3268,8 +3264,7 @@ "@ vperm %0,%1,%2,%3 xxperm %x0,%x1,%x3" - [(set_attr "type" "vecperm") - (set_attr "length" "4")]) + [(set_attr "type" "vecperm")]) (define_insn "vperm_v16qiv8hi" [(set (match_operand:V8HI 0 "register_operand" "=v,?wo") @@ -3281,8 +3276,7 @@ "@ vperm %0,%1,%2,%3 xxperm %x0,%x1,%x3" - [(set_attr "type" "vecperm") - (set_attr "length" "4")]) + [(set_attr "type" "vecperm")]) (define_expand "vec_unpacku_hi_v16qi" @@ -3857,8 +3851,7 @@ (clz:VI2 (match_operand:VI2 1 "register_operand" "v")))] "TARGET_P8_VECTOR" "vclz %0,%1" - [(set_attr "length" "4") - (set_attr "type" "vecsimple")]) + [(set_attr "type" "vecsimple")]) ;; Vector absolute difference unsigned (define_expand "vadu3" @@ -3884,8 +3877,7 @@ (ctz:VI2 (match_operand:VI2 1 "register_operand" "v")))] "TARGET_P9_VECTOR" "vctz %0,%1" - [(set_attr "length" "4") - (set_attr "type" "vecsimple")]) + [(set_attr "type" "vecsimple")]) ;; Vector population count (define_insn "*p8v_popcount2" @@ -3893,8 +3885,7 @@ (popcount:VI2 (match_operand:VI2 1 "register_operand" "v")))] "TARGET_P8_VECTOR" "vpopcnt %0,%1" - [(set_attr "length" "4") - (set_attr "type" "vecsimple")]) + [(set_attr "type" "vecsimple")]) ;; Vector parity (define_insn "*p9v_parity2" @@ -3902,8 +3893,7 @@ (parity:VParity (match_operand:VParity 1 "register_operand" "v")))] "TARGET_P9_VECTOR" "vprtyb %0,%1" - [(set_attr "length" "4") - (set_attr "type" "vecsimple")]) + [(set_attr "type" "vecsimple")]) ;; Vector Gather Bits by Bytes by Doubleword (define_insn "p8v_vgbbd" @@ -3912,8 +3902,7 @@ UNSPEC_VGBBD))] "TARGET_P8_VECTOR" "vgbbd %0,%1" - [(set_attr "length" "4") - (set_attr "type" "vecsimple")]) + [(set_attr "type" "vecsimple")]) ;; 128-bit binary integer arithmetic @@ -3927,8 +3916,7 @@ (match_operand:V1TI 2 "register_operand" "v")))] "TARGET_VADDUQM" "vadduqm %0,%1,%2" - [(set_attr "length" "4") - (set_attr "type" "vecsimple")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vaddcuq" [(set (match_operand:V1TI 0 "register_operand" "=v") @@ -3937,8 +3925,7 @@ UNSPEC_VADDCUQ))] "TARGET_VADDUQM" "vaddcuq %0,%1,%2" - [(set_attr "length" "4") - (set_attr "type" "vecsimple")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vsubuqm" [(set (match_operand:V1TI 0 "register_operand" "=v") @@ -3946,8 +3933,7 @@ (match_operand:V1TI 2 "register_operand" "v")))] "TARGET_VADDUQM" "vsubuqm %0,%1,%2" - [(set_attr "length" "4") - (set_attr "type" "vecsimple")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vsubcuq" [(set (match_operand:V1TI 0 "register_operand" "=v") @@ -3956,8 +3942,7 @@ UNSPEC_VSUBCUQ))] "TARGET_VADDUQM" "vsubcuq %0,%1,%2" - [(set_attr "length" "4") - (set_attr "type" "vecsimple")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vaddeuqm" [(set (match_operand:V1TI 0 "register_operand" "=v") @@ -3967,8 +3952,7 @@ UNSPEC_VADDEUQM))] "TARGET_VADDUQM" "vaddeuqm %0,%1,%2,%3" - [(set_attr "length" "4") - (set_attr "type" "vecsimple")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vaddecuq" [(set (match_operand:V1TI 0 "register_operand" "=v") @@ -3978,8 +3962,7 @@ UNSPEC_VADDECUQ))] "TARGET_VADDUQM" "vaddecuq %0,%1,%2,%3" - [(set_attr "length" "4") - (set_attr "type" "vecsimple")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vsubeuqm" [(set (match_operand:V1TI 0 "register_operand" "=v") @@ -3989,8 +3972,7 @@ UNSPEC_VSUBEUQM))] "TARGET_VADDUQM" "vsubeuqm %0,%1,%2,%3" - [(set_attr "length" "4") - (set_attr "type" "vecsimple")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vsubecuq" [(set (match_operand:V1TI 0 "register_operand" "=v") @@ -4000,8 +3982,7 @@ UNSPEC_VSUBECUQ))] "TARGET_VADDUQM" "vsubecuq %0,%1,%2,%3" - [(set_attr "length" "4") - (set_attr "type" "vecsimple")]) + [(set_attr "type" "vecsimple")]) ;; We use V2DI as the output type to simplify converting the permute ;; bits into an integer @@ -4093,8 +4074,7 @@ (clobber (reg:CCFP CR6_REGNO))] "TARGET_P8_VECTOR" "bcd. %0,%1,%2,%3" - [(set_attr "length" "4") - (set_attr "type" "vecsimple")]) + [(set_attr "type" "vecsimple")]) ;; Use a floating point type (V2DFmode) for the compare to set CR6 so that we ;; can use the unordered test for BCD nans and add/subtracts that overflow. An @@ -4112,8 +4092,7 @@ (clobber (match_scratch:V1TI 0 "=v"))] "TARGET_P8_VECTOR" "bcd. %0,%1,%2,%3" - [(set_attr "length" "4") - (set_attr "type" "vecsimple")]) + [(set_attr "type" "vecsimple")]) (define_insn "*bcd_test2" [(set (match_operand:V1TI 0 "register_operand" "=v") @@ -4130,8 +4109,7 @@ (match_operand:V2DF 4 "zero_constant" "j")))] "TARGET_P8_VECTOR" "bcd. %0,%1,%2,%3" - [(set_attr "length" "4") - (set_attr "type" "vecsimple")]) + [(set_attr "type" "vecsimple")]) (define_insn "darn_32" [(set (match_operand:SI 0 "register_operand" "=r") diff --git a/gcc/config/rs6000/darwin.md b/gcc/config/rs6000/darwin.md index 7c429a5e180..37acb312b4b 100644 --- a/gcc/config/rs6000/darwin.md +++ b/gcc/config/rs6000/darwin.md @@ -23,8 +23,7 @@ You should have received a copy of the GNU General Public License (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b") (high:DI (match_operand 2 "" ""))))] "TARGET_MACHO && TARGET_64BIT" - "addis %0,%1,ha16(%2)" - [(set_attr "length" "4")]) + "addis %0,%1,ha16(%2)") (define_insn "movdf_low_si" [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r") @@ -72,8 +71,7 @@ You should have received a copy of the GNU General Public License gcc_unreachable (); } } - [(set_attr "type" "load") - (set_attr "length" "4,4")]) + [(set_attr "type" "load")]) (define_insn "movdf_low_st_si" [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") @@ -81,8 +79,7 @@ You should have received a copy of the GNU General Public License (match_operand:DF 0 "gpc_reg_operand" "f"))] "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT" "stfd %0,lo16(%2)(%1)" - [(set_attr "type" "store") - (set_attr "length" "4")]) + [(set_attr "type" "store")]) (define_insn "movdf_low_st_di" [(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b") @@ -90,8 +87,7 @@ You should have received a copy of the GNU General Public License (match_operand:DF 0 "gpc_reg_operand" "f"))] "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT" "stfd %0,lo16(%2)(%1)" - [(set_attr "type" "store") - (set_attr "length" "4")]) + [(set_attr "type" "store")]) (define_insn "movsf_low_si" [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r") @@ -101,8 +97,7 @@ You should have received a copy of the GNU General Public License "@ lfs %0,lo16(%2)(%1) lwz %0,lo16(%2)(%1)" - [(set_attr "type" "load") - (set_attr "length" "4")]) + [(set_attr "type" "load")]) (define_insn "movsf_low_di" [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r") @@ -112,8 +107,7 @@ You should have received a copy of the GNU General Public License "@ lfs %0,lo16(%2)(%1) lwz %0,lo16(%2)(%1)" - [(set_attr "type" "load") - (set_attr "length" "4")]) + [(set_attr "type" "load")]) (define_insn "movsf_low_st_si" [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") @@ -123,8 +117,7 @@ You should have received a copy of the GNU General Public License "@ stfs %0,lo16(%2)(%1) stw %0,lo16(%2)(%1)" - [(set_attr "type" "store") - (set_attr "length" "4")]) + [(set_attr "type" "store")]) (define_insn "movsf_low_st_di" [(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") @@ -134,8 +127,7 @@ You should have received a copy of the GNU General Public License "@ stfs %0,lo16(%2)(%1) stw %0,lo16(%2)(%1)" - [(set_attr "type" "store") - (set_attr "length" "4")]) + [(set_attr "type" "store")]) ;; 64-bit MachO load/store support (define_insn "movdi_low" @@ -146,8 +138,7 @@ You should have received a copy of the GNU General Public License "@ ld %0,lo16(%2)(%1) lfd %0,lo16(%2)(%1)" - [(set_attr "type" "load") - (set_attr "length" "4")]) + [(set_attr "type" "load")]) (define_insn "movsi_low_st" [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") @@ -155,8 +146,7 @@ You should have received a copy of the GNU General Public License (match_operand:SI 0 "gpc_reg_operand" "r"))] "TARGET_MACHO && ! TARGET_64BIT" "stw %0,lo16(%2)(%1)" - [(set_attr "type" "store") - (set_attr "length" "4")]) + [(set_attr "type" "store")]) (define_insn "movdi_low_st" [(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") @@ -166,8 +156,7 @@ You should have received a copy of the GNU General Public License "@ std %0,lo16(%2)(%1) stfd %0,lo16(%2)(%1)" - [(set_attr "type" "store") - (set_attr "length" "4")]) + [(set_attr "type" "store")]) ;; Mach-O PIC trickery. (define_expand "macho_high" diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md index cd15aa81bfd..9bc98f978a5 100644 --- a/gcc/config/rs6000/dfp.md +++ b/gcc/config/rs6000/dfp.md @@ -37,8 +37,7 @@ || gpc_reg_operand (operands[1], SDmode)) && TARGET_HARD_FLOAT" "stfd%U0%X0 %1,%0" - [(set_attr "type" "fpstore") - (set_attr "length" "4")]) + [(set_attr "type" "fpstore")]) (define_insn "movsd_load" [(set (match_operand:SD 0 "nonimmediate_operand" "=f") @@ -48,8 +47,7 @@ || gpc_reg_operand (operands[1], DDmode)) && TARGET_HARD_FLOAT" "lfd%U1%X1 %0,%1" - [(set_attr "type" "fpload") - (set_attr "length" "4")]) + [(set_attr "type" "fpload")]) ;; Hardware support for decimal floating point operations. diff --git a/gcc/config/rs6000/htm.md b/gcc/config/rs6000/htm.md index 44a52c5be8b..96c8288285b 100644 --- a/gcc/config/rs6000/htm.md +++ b/gcc/config/rs6000/htm.md @@ -72,8 +72,7 @@ (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))] "TARGET_HTM" "tabort. %0" - [(set_attr "type" "htmsimple") - (set_attr "length" "4")]) + [(set_attr "type" "htmsimple")]) (define_expand "tabortc" [(parallel @@ -98,8 +97,7 @@ (set (match_operand:BLK 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))] "TARGET_HTM" "tabortc. %0,%1,%2" - [(set_attr "type" "htmsimple") - (set_attr "length" "4")]) + [(set_attr "type" "htmsimple")]) (define_expand "tabortci" [(parallel @@ -124,8 +122,7 @@ (set (match_operand:BLK 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))] "TARGET_HTM" "tabortci. %0,%1,%2" - [(set_attr "type" "htmsimple") - (set_attr "length" "4")]) + [(set_attr "type" "htmsimple")]) (define_expand "tbegin" [(parallel @@ -146,8 +143,7 @@ (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))] "TARGET_HTM" "tbegin. %0" - [(set_attr "type" "htm") - (set_attr "length" "4")]) + [(set_attr "type" "htm")]) (define_expand "tcheck" [(parallel @@ -166,8 +162,7 @@ (set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))] "TARGET_HTM" "tcheck %0" - [(set_attr "type" "htm") - (set_attr "length" "4")]) + [(set_attr "type" "htm")]) (define_expand "tend" [(parallel @@ -188,8 +183,7 @@ (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))] "TARGET_HTM" "tend. %0" - [(set_attr "type" "htm") - (set_attr "length" "4")]) + [(set_attr "type" "htm")]) (define_expand "trechkpt" [(parallel @@ -208,8 +202,7 @@ (set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))] "TARGET_HTM" "trechkpt." - [(set_attr "type" "htmsimple") - (set_attr "length" "4")]) + [(set_attr "type" "htmsimple")]) (define_expand "treclaim" [(parallel @@ -230,8 +223,7 @@ (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))] "TARGET_HTM" "treclaim. %0" - [(set_attr "type" "htmsimple") - (set_attr "length" "4")]) + [(set_attr "type" "htmsimple")]) (define_expand "tsr" [(parallel @@ -252,8 +244,7 @@ (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))] "TARGET_HTM" "tsr. %0" - [(set_attr "type" "htmsimple") - (set_attr "length" "4")]) + [(set_attr "type" "htmsimple")]) (define_expand "ttest" [(parallel @@ -272,8 +263,7 @@ (set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))] "TARGET_HTM" "tabortwci. 0,1,0" - [(set_attr "type" "htmsimple") - (set_attr "length" "4")]) + [(set_attr "type" "htmsimple")]) (define_insn "htm_mfspr_" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") @@ -282,8 +272,7 @@ UNSPECV_HTM_MFSPR))] "TARGET_HTM" "mfspr %0,%1"; - [(set_attr "type" "htm") - (set_attr "length" "4")]) + [(set_attr "type" "htm")]) (define_insn "htm_mtspr_" [(set (match_operand:GPR 2 "htm_spr_reg_operand" "") @@ -292,5 +281,4 @@ UNSPECV_HTM_MTSPR))] "TARGET_HTM" "mtspr %1,%0"; - [(set_attr "type" "htm") - (set_attr "length" "4")]) + [(set_attr "type" "htm")]) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index c066baeeecc..50c264f0dc1 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -2378,8 +2378,7 @@ (bswap:HSI (match_operand:HSI 1 "memory_operand" "Z"))))] "TARGET_POWERPC64" "lbrx %0,%y1" - [(set_attr "length" "4") - (set_attr "type" "load")]) + [(set_attr "type" "load")]) (define_insn "*bswaphi2_extendsi" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -2387,8 +2386,7 @@ (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))] "" "lhbrx %0,%y1" - [(set_attr "length" "4") - (set_attr "type" "load")]) + [(set_attr "type" "load")]) ;; Separate the bswap patterns into load, store, and gpr<-gpr. This prevents ;; the register allocator from converting a gpr<-gpr swap into a store and then @@ -6080,8 +6078,7 @@ "@ fcfidu %0,%1 xscvuxddp %x0,%x1" - [(set_attr "type" "fp") - (set_attr "length" "4")]) + [(set_attr "type" "fp")]) (define_insn_and_split "*floatunsdidf2_mem" [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws") @@ -6696,8 +6693,7 @@ (match_operand 2 "" ""))))] "TARGET_MACHO && ! TARGET_64BIT" "lwz %0,lo16(%2)(%1)" - [(set_attr "type" "load") - (set_attr "length" "4")]) + [(set_attr "type" "load")]) ;; MR LA LWZ LFIWZX LXSIWZX ;; STW STFIWX STXSIWX LI LIS @@ -9407,8 +9403,7 @@ (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] UNSPEC_TLSGD)))] "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL" - "addis %0,%1,%2@got@tlsgd@ha" - [(set_attr "length" "4")]) + "addis %0,%1,%2@got@tlsgd@ha") (define_insn "*tls_gd_low" [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") @@ -9417,8 +9412,7 @@ (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] UNSPEC_TLSGD)))] "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL" - "addi %0,%1,%2@got@tlsgd@l" - [(set_attr "length" "4")]) + "addi %0,%1,%2@got@tlsgd@l") (define_insn "*tls_gd_call_aix" [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") @@ -9542,8 +9536,7 @@ (match_operand:TLSmode 1 "gpc_reg_operand" "b")] UNSPEC_TLSLD)))] "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL" - "addis %0,%1,%&@got@tlsld@ha" - [(set_attr "length" "4")]) + "addis %0,%1,%&@got@tlsld@ha") (define_insn "*tls_ld_low" [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") @@ -9552,8 +9545,7 @@ (match_operand:TLSmode 2 "gpc_reg_operand" "b")] UNSPEC_TLSLD)))] "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL" - "addi %0,%1,%&@got@tlsld@l" - [(set_attr "length" "4")]) + "addi %0,%1,%&@got@tlsld@l") (define_insn "*tls_ld_call_aix" [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") @@ -9638,8 +9630,7 @@ (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] UNSPEC_TLSGOTDTPREL)))] "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL" - "addis %0,%1,%2@got@dtprel@ha" - [(set_attr "length" "4")]) + "addis %0,%1,%2@got@dtprel@ha") (define_insn "*tls_got_dtprel_low" [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") @@ -9648,8 +9639,7 @@ (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] UNSPEC_TLSGOTDTPREL)))] "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL" - "l %0,%2@got@dtprel@l(%1)" - [(set_attr "length" "4")]) + "l %0,%2@got@dtprel@l(%1)") (define_insn "tls_tprel_" [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") @@ -9707,8 +9697,7 @@ (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] UNSPEC_TLSGOTTPREL)))] "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL" - "addis %0,%1,%2@got@tprel@ha" - [(set_attr "length" "4")]) + "addis %0,%1,%2@got@tprel@ha") (define_insn "*tls_got_tprel_low" [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") @@ -9717,8 +9706,7 @@ (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] UNSPEC_TLSGOTTPREL)))] "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL" - "l %0,%2@got@tprel@l(%1)" - [(set_attr "length" "4")]) + "l %0,%2@got@tprel@l(%1)") (define_insn "tls_tls_" [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") @@ -11098,8 +11086,7 @@ (set (attr "indexed") (if_then_else (match_operand 0 "indexed_address_mem") (const_string "yes") - (const_string "no"))) - (set_attr "length" "4")]) + (const_string "no")))]) (define_insn "probe_stack_range" [(set (match_operand:P 0 "register_operand" "=&r") @@ -12347,8 +12334,7 @@ { return output_cbranch (operands[0], NULL, 0, insn); } - [(set_attr "type" "jmpreg") - (set_attr "length" "4")]) + [(set_attr "type" "jmpreg")]) ;; Logic on condition register values. @@ -13859,8 +13845,7 @@ UNSPEC_ADDG6S))] "TARGET_POPCNTD" "addg6s %0,%1,%2" - [(set_attr "type" "integer") - (set_attr "length" "4")]) + [(set_attr "type" "integer")]) (define_insn "cdtbcd" [(set (match_operand:SI 0 "register_operand" "=r") @@ -13868,8 +13853,7 @@ UNSPEC_CDTBCD))] "TARGET_POPCNTD" "cdtbcd %0,%1" - [(set_attr "type" "integer") - (set_attr "length" "4")]) + [(set_attr "type" "integer")]) (define_insn "cbcdtd" [(set (match_operand:SI 0 "register_operand" "=r") @@ -13877,8 +13861,7 @@ UNSPEC_CBCDTD))] "TARGET_POPCNTD" "cbcdtd %0,%1" - [(set_attr "type" "integer") - (set_attr "length" "4")]) + [(set_attr "type" "integer")]) (define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE UNSPEC_DIVEU]) @@ -13935,8 +13918,7 @@ operands[3] = gen_rtx_REG (mode, fp_regno); } - [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store") - (set_attr "length" "4")]) + [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store")]) (define_insn_and_split "unpack_nodm" [(set (match_operand: 0 "nonimmediate_operand" "=d,m") @@ -13959,8 +13941,7 @@ operands[3] = gen_rtx_REG (mode, fp_regno); } - [(set_attr "type" "fp,fpstore") - (set_attr "length" "4")]) + [(set_attr "type" "fp,fpstore")]) (define_insn_and_split "pack" [(set (match_operand:FMOVE128 0 "register_operand" "=&d") diff --git a/gcc/config/rs6000/sync.md b/gcc/config/rs6000/sync.md index 74bc407b462..ee98049cdd8 100644 --- a/gcc/config/rs6000/sync.md +++ b/gcc/config/rs6000/sync.md @@ -132,8 +132,7 @@ "TARGET_SYNC_TI && !reg_mentioned_p (operands[0], operands[1])" "lq %0,%1" - [(set_attr "type" "load") - (set_attr "length" "4")]) + [(set_attr "type" "load")]) (define_expand "atomic_load" [(set (match_operand:AINT 0 "register_operand") ;; output @@ -196,8 +195,7 @@ [(match_operand:PTI 1 "quad_int_reg_operand" "r")] UNSPEC_LSQ))] "TARGET_SYNC_TI" "stq %1,%0" - [(set_attr "type" "store") - (set_attr "length" "4")]) + [(set_attr "type" "store")]) (define_expand "atomic_store" [(set (match_operand:AINT 0 "memory_operand") ;; memory diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index de2fa7815a3..c3c099f40e9 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3267,8 +3267,7 @@ stfd%U0%X0 %1,%0 stxsd%U0x %x1,%y0 stxsd %1,%0" - [(set_attr "type" "fpstore") - (set_attr "length" "4")]) + [(set_attr "type" "fpstore")]) ;; Variable V2DI/V2DF extract shift (define_insn "vsx_vslo_" -- 2.30.2