From b265874dee486343ebe8d86be5b3224f6108a8e7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 19 Apr 2021 16:40:46 +0100 Subject: [PATCH] add some links to crypto page --- crypto_router_asic.mdwn | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/crypto_router_asic.mdwn b/crypto_router_asic.mdwn index cd6524927..1cecf298c 100644 --- a/crypto_router_asic.mdwn +++ b/crypto_router_asic.mdwn @@ -7,16 +7,21 @@ All of these are entirely Libre-Licensed: -* 300 mhz single-core, Libre-SOC OpenPOWER CPU +* 300 mhz single-core, + [Libre-SOC](https://git.libre-soc.org/?p=soc.git;a=blob;f=README.md;hb=HEAD) + OpenPOWER CPU with + [[openpower/sv/bitmanip]] extensions * 180/130 nm (TBD) -* 5x [[RGMII]] Gigabit Ethernet PHYs -* 2x USB [[ULPI]] PHYs +* 5x [[shakhti/m_class/RGMII]] Gigabit Ethernet PHYs +* 2x USB [[shakhti/m_class/ULPI]] PHYs * Direct DMA interface (independent bulk transfer) -* JTAG, GPIO, I2C, PWM, UART, SPI, QSPI, SD/MMC +* [JTAG](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtag.py;hb=HEAD), + GPIO, I2C, PWM, UART, SPI, QSPI, SD/MMC * On-board Dual-ported SRAM (for Packet Buffers) -* Opencores [[sdram]] +* Opencores [[shakhti/m_class/sdram]] * Wishbone interfaces to all peripherals -* XICS ICP / ICS Interrupt Controller +* [XICS ICP / ICS](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/interrupts/xics.py;hb=HEAD) + Interrupt Controller # Example packet transfer: -- 2.30.2