From b2672aebd8aac9aac3a2769b9a0ce509e86b0da6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 2 May 2019 15:36:48 +0100 Subject: [PATCH] get test_add working after reorg --- src/ieee754/fpadd/pipeline.py | 2 +- src/ieee754/fpadd/test/test_add.py | 2 +- src/{ieee754/add => nmutil}/concurrentunit.py | 0 3 files changed, 2 insertions(+), 2 deletions(-) rename src/{ieee754/add => nmutil}/concurrentunit.py (100%) diff --git a/src/ieee754/fpadd/pipeline.py b/src/ieee754/fpadd/pipeline.py index eea89355..7b37a687 100644 --- a/src/ieee754/fpadd/pipeline.py +++ b/src/ieee754/fpadd/pipeline.py @@ -8,6 +8,7 @@ from nmigen.cli import main, verilog from nmutil.singlepipe import (ControlBase, SimpleHandshake, PassThroughStage) from nmutil.multipipe import CombMuxOutPipe from nmutil.multipipe import PriorityCombMuxInPipe +from nmutil.concurrentunit import ReservationStations, num_bits from ieee754.fpcommon.getop import FPADDBaseData from ieee754.fpcommon.denorm import FPSCData @@ -16,7 +17,6 @@ from ieee754.fpcommon.normtopack import FPNormToPack from .specialcases import FPAddSpecialCasesDeNorm from .addstages import FPAddAlignSingleAdd -from concurrentunit import ReservationStations, num_bits class FPADDBasePipe(ControlBase): diff --git a/src/ieee754/fpadd/test/test_add.py b/src/ieee754/fpadd/test/test_add.py index 35503bed..f09804cd 100644 --- a/src/ieee754/fpadd/test/test_add.py +++ b/src/ieee754/fpadd/test/test_add.py @@ -5,7 +5,7 @@ from nmigen.compat.sim import run_simulation from ieee754.fpadd.nmigen_add_experiment import FPADD -from iee754.fpcommon.unit_test_single import (get_mantissa, get_exponent, +from ieee754.fpcommon.test.unit_test_single import (get_mantissa, get_exponent, get_sign, is_nan, is_inf, is_pos_inf, is_neg_inf, match, get_rs_case, check_rs_case, run_test, diff --git a/src/ieee754/add/concurrentunit.py b/src/nmutil/concurrentunit.py similarity index 100% rename from src/ieee754/add/concurrentunit.py rename to src/nmutil/concurrentunit.py -- 2.30.2