From b291a3a4a313851f3f88247c3c6c8a0dc4499a77 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Samuel=20Iglesias=20Gons=C3=A1lvez?= Date: Wed, 25 Apr 2018 11:55:49 +0200 Subject: [PATCH] spirv: convert some operands for bitwise shift and bitwise ops to uint32 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit SPIR-V allows to define the shift, offset and count operands for shift and bitfield opcodes with a bit-size different than 32 bits, but in NIR the opcodes have that limitation. As agreed in the mailing list, this patch adds a conversion to 32 bits to fix this. For more info, see: https://lists.freedesktop.org/archives/mesa-dev/2018-April/193026.html v2: - src_bit_size will have zero value for variable bit-size operands (Jason). Signed-off-by: Samuel Iglesias Gonsálvez Reviewed-by: Jason Ekstrand --- src/compiler/spirv/vtn_alu.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c index 3134849ba90..b6f98483ec6 100644 --- a/src/compiler/spirv/vtn_alu.c +++ b/src/compiler/spirv/vtn_alu.c @@ -635,6 +635,41 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode, break; } + case SpvOpBitFieldInsert: + case SpvOpBitFieldSExtract: + case SpvOpBitFieldUExtract: + case SpvOpShiftLeftLogical: + case SpvOpShiftRightArithmetic: + case SpvOpShiftRightLogical: { + bool swap; + unsigned src0_bit_size = glsl_get_bit_size(vtn_src[0]->type); + unsigned dst_bit_size = glsl_get_bit_size(type); + nir_op op = vtn_nir_alu_op_for_spirv_opcode(b, opcode, &swap, + src0_bit_size, dst_bit_size); + + assert (op == nir_op_ushr || op == nir_op_ishr || op == nir_op_ishl || + op == nir_op_bitfield_insert || op == nir_op_ubitfield_extract || + op == nir_op_ibitfield_extract); + + for (unsigned i = 0; i < nir_op_infos[op].num_inputs; i++) { + unsigned src_bit_size = + nir_alu_type_get_type_size(nir_op_infos[op].input_types[i]); + if (src_bit_size == 0) + continue; + if (src_bit_size != src[i]->bit_size) { + assert(src_bit_size == 32); + /* Convert the Shift, Offset and Count operands to 32 bits, which is the bitsize + * supported by the NIR instructions. See discussion here: + * + * https://lists.freedesktop.org/archives/mesa-dev/2018-April/193026.html + */ + src[i] = nir_u2u32(&b->nb, src[i]); + } + } + val->ssa->def = nir_build_alu(&b->nb, op, src[0], src[1], src[2], src[3]); + break; + } + default: { bool swap; unsigned src_bit_size = glsl_get_bit_size(vtn_src[0]->type); -- 2.30.2