From b293aca2cc5a8585e064161d77d98a2b7556a92d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Jun 2020 17:28:46 +0100 Subject: [PATCH] move reg setup to earlier in test --- src/soc/simple/test/test_core.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index 6a3f5cb2..877c215e 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -137,6 +137,10 @@ class TestRunner(FHDLTestCase): gen = program.generate_instructions() instructions = list(zip(gen, program.assembly.splitlines())) + # set up INT regfile, "direct" write from sim data + for i in range(32): + yield core.regs.int.regs[i].reg.eq(test.regs[i]) + index = sim.pc.CIA.value//4 while index < len(instructions): ins, code = instructions[index] @@ -157,10 +161,6 @@ class TestRunner(FHDLTestCase): yield from set_issue(core, pdecode2, sim) yield Settle() - # set up INT regfile, "direct" write from sim data - for i in range(32): - yield core.regs.int.regs[i].reg.eq(test.regs[i]) - yield from wait_for_busy_clear(core) yield core.ivalid_i.eq(0) -- 2.30.2