From b2a44cde6468fb6065169194fe3a67b2f4738b71 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 18 Jul 2012 22:58:15 -0700 Subject: [PATCH] i965/gen7: Increase the WM threads to hardware limits. This thread count is only supposed to be enabled when "WIZ Hashing Disable in GT_MODE register enabled." I've always been confused whether that means the bit in the register should be 1 or 0. For my IVB GT2's register 0x7008 value of 0x0, this appears to work fine. Improves l4d2 performance at 640x480 by 0.88 +/- 0.11% (n=88). Improves performance with rasterization at 1280x1024 by 1.45% +/- 0.36% (n=6). Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_context.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index f5c8b6eea6d..5a109e30430 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -248,7 +248,7 @@ brwCreateContext(int api, brw->urb.max_vs_entries = 512; brw->urb.max_gs_entries = 192; } else if (intel->gt == 2) { - brw->max_wm_threads = 86; + brw->max_wm_threads = 172; brw->max_vs_threads = 128; brw->max_gs_threads = 128; brw->urb.size = 256; -- 2.30.2