From b2c66b1efd6bd056c26ebd85e9a8ccd2e53e15e0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 11 Feb 2020 16:39:37 +0100 Subject: [PATCH] soc: avoid double definition of main_ram --- litex/soc/integration/soc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index f20d6ecb..42eab475 100755 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -958,7 +958,7 @@ class LiteXSoC(SoC): elif self.with_wishbone: # Wishbone Slave SDRAM interface ------------------------------------------------------- wb_sdram = wishbone.Interface() - self.bus.add_slave("main_ram", wb_sdram, SoCRegion(origin=origin, size=sdram_size)) + self.bus.add_slave("main_ram", wb_sdram) # L2 Cache ----------------------------------------------------------------------------- if l2_cache_size != 0: -- 2.30.2