From b2ce34237fea8b79ba1168c4aa142deb190ba5f8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 18 Sep 2022 21:20:00 +0100 Subject: [PATCH] correct COopFF3RM and CRopSimpleRM: extra sz field and sz/dz/zz bit 6 --- src/openpower/decoder/power_insn.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index 1ef94d38..47ee25eb 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -1658,7 +1658,6 @@ class CROpBaseRM(BaseRM): class CROpSimpleRM(MRBaseRM, DZBaseRM, SZBaseRM, CROpBaseRM): """cr_op: simple mode""" RG: BaseRM[20] - sz: BaseRM[21] dz: BaseRM[22] sz: BaseRM[23] @@ -1675,8 +1674,9 @@ class CROpFF3RM(ZZBaseRM, CROpBaseRM): VLI: BaseRM[20] inv: BaseRM[21] CR: BaseRM[22, 23] - sz: BaseRM[21] - dz: BaseRM[22] + zz: BaseRM[6] + sz: BaseRM[6] + dz: BaseRM[6] def specifiers(self, record): yield from super().specifiers(record=record, mode="ff") -- 2.30.2