From b2eb17c54da96fadf5eec01585c9b5983d654efb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 7 Jun 2020 14:42:26 +0100 Subject: [PATCH] add extra args to ISA in test_pipe_caller.py --- src/soc/fu/shift_rot/test/test_pipe_caller.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py index c8e3153e..1e09224d 100644 --- a/src/soc/fu/shift_rot/test/test_pipe_caller.py +++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py @@ -229,7 +229,8 @@ class TestRunner(FHDLTestCase): print(test.name) program = test.program self.subTest(test.name) - simulator = ISA(pdecode2, test.regs, test.sprs, 0) + simulator = ISA(pdecode2, test.regs, test.sprs, test.cr, + test.mem, test.msr) gen = program.generate_instructions() instructions = list(zip(gen, program.assembly.splitlines())) -- 2.30.2