From b3133e66c849eff228f98f1d306a6bf9dc12edb8 Mon Sep 17 00:00:00 2001
From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Wed, 15 Jul 2020 12:44:41 +0200
Subject: [PATCH] Increase UART bridge speed in simulation, decrease simulation
 time

---
 gram/simulation/simsoc.py  |  2 +-
 gram/simulation/simsoctb.v | 12 ++++++------
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/gram/simulation/simsoc.py b/gram/simulation/simsoc.py
index e008935..486b831 100644
--- a/gram/simulation/simsoc.py
+++ b/gram/simulation/simsoc.py
@@ -26,7 +26,7 @@ class DDR3SoC(SoC, Elaboratable):
         self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
                                          features={"cti", "bte"})
 
-        self.ub = UARTBridge(divisor=217, pins=platform.request("uart", 0))
+        self.ub = UARTBridge(divisor=5, pins=platform.request("uart", 0))
         self._arbiter.add(self.ub.bus)
 
         self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"})))
diff --git a/gram/simulation/simsoctb.v b/gram/simulation/simsoctb.v
index 74395a1..ac8bdbd 100644
--- a/gram/simulation/simsoctb.v
+++ b/gram/simulation/simsoctb.v
@@ -114,7 +114,7 @@ module simsoctb;
     begin
       uart_rx <= 1'b1;
       $display("[%t] Starting POR",$time);
-      #100; // POR is ~700us
+      #1000; // POR is ~700us
       $display("[%t] POR complete",$time);
 
       // Software control
@@ -216,14 +216,14 @@ module simsoctb;
 
     begin
       uart_rx <= 1'b0;
-      #2170;
+      #50;
       for (i = 0; i < 8; i = i + 1)
         begin
           uart_rx <= data[i];
-          #2170;
+          #50;
         end
       uart_rx <= 1'b1;
-      #2170;
+      #50;
     end
   endtask
 
@@ -239,10 +239,10 @@ module simsoctb;
 
       for (i = 0; i < 8; i = i+1)
         begin
-          #2170 data[i] <= uart_tx;
+          #50 data[i] <= uart_tx;
         end
 
-      #2170;
+      #50;
     end
   endtask
 endmodule
-- 
2.30.2