From b313772a0cae003f4e02675ec6bf42f70fd6c56a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 29 Mar 2015 12:34:40 +0200 Subject: [PATCH] sdram: remove redundant with_l2 parameter (equivalent to l2_size != 0) --- misoclib/mem/sdram/core/lasmicon/__init__.py | 3 +-- misoclib/soc/sdram.py | 4 ++-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/misoclib/mem/sdram/core/lasmicon/__init__.py b/misoclib/mem/sdram/core/lasmicon/__init__.py index ed199a02..e61973ca 100644 --- a/misoclib/mem/sdram/core/lasmicon/__init__.py +++ b/misoclib/mem/sdram/core/lasmicon/__init__.py @@ -9,14 +9,13 @@ from misoclib.mem.sdram.core.lasmicon.multiplexer import * class LASMIconSettings: def __init__(self, req_queue_size=8, read_time=32, write_time=16, - with_l2=True, l2_size=8192, + l2_size=8192, with_bandwidth=False, with_memtest=False, with_refresh=True): self.req_queue_size = req_queue_size self.read_time = read_time self.write_time = write_time - self.with_l2 = with_l2 self.l2_size = l2_size if with_memtest: self.with_bandwidth = True diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py index 72f82f78..e8227c95 100644 --- a/misoclib/soc/sdram.py +++ b/misoclib/soc/sdram.py @@ -53,8 +53,8 @@ class SDRAMSoC(SoC): self.submodules.memtest_w = memtest.MemtestWriter(self.sdram.crossbar.get_master()) self.submodules.memtest_r = memtest.MemtestReader(self.sdram.crossbar.get_master()) - if self.sdram_controller_settings.with_l2: - l2_size = self.sdram_controller_settings.l2_size + l2_size = self.sdram_controller_settings.l2_size + if l2_size != 0: # XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache. # Issue is reported to Xilinx and should be fixed in next releases (2015.1?). # Remove this workaround when fixed by Xilinx. -- 2.30.2