From b3569e74451e3b913a2f3b327db430edbcd8f42e Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Tue, 6 Jun 2017 20:58:31 -0700 Subject: [PATCH] i965: Disable the interleaved vertex optimization when instancing MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Instance divisor is a property of the vertex buffer and not the vertex element so if we ever see anything other than 0, bail. Cc: "17.1" Reviewed-by: Samuel Iglesias Gonsálvez --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 2ec9a013cd9..cf667709165 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -584,15 +584,16 @@ brw_prepare_vertices(struct brw_context *brw) ptr = glarray->Ptr; } else if (interleaved != glarray->StrideB || + glarray->InstanceDivisor != 0 || glarray->Ptr < ptr || (uintptr_t)(glarray->Ptr - ptr) + glarray->_ElementSize > interleaved) { /* If our stride is different from the first attribute's stride, - * or if the first attribute's stride didn't cover our element, - * disable the interleaved upload optimization. The second case - * can most commonly occur in cases where there is a single vertex - * and, for example, the data is stored on the application's - * stack. + * or if we are using an instance divisor or if the first + * attribute's stride didn't cover our element, disable the + * interleaved upload optimization. The second case can most + * commonly occur in cases where there is a single vertex and, for + * example, the data is stored on the application's stack. * * NOTE: This will also disable the optimization in cases where * the data is in a different order than the array indices. -- 2.30.2