From b36fd8d1079ce0fcd77eb3b13145b9c0664fef8c Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 21 Aug 2022 17:52:19 +0100 Subject: [PATCH] --- openpower/sv/svp64/appendix.mdwn | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index 4a15058a9..13b27ff73 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -909,7 +909,7 @@ Instructions are broken down by Register Profiles as listed in the following auto-generated page: [[opcode_regs_deduped]]. These tables, despite being auto-generated, are part of the Specification. -# SV pseudocode illilustration +# SV pseudocode illustration ## Single-predicated Instruction @@ -927,8 +927,7 @@ overrides not included. if there is no predicate, it is set to all 1s if (rd.isvec) { id += 1; } if (rs1.isvec) { irs1 += 1; } if (rs2.isvec) { irs2 += 1; } - if (id == VL or irs1 == VL or irs2 == VL) - { + if (id == VL or irs1 == VL or irs2 == VL) { # end VL hardware loop STATE.srcoffs = 0; # reset return; -- 2.30.2