From b3707067602aa59d02c16e207be9a0254a14df15 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 18 Dec 2021 15:37:34 +0000 Subject: [PATCH] use new core domain variable in TestRunnerBase and add the dbgsync domain back in --- src/openpower/test/runner.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py index cc91b75d..1bce1f39 100644 --- a/src/openpower/test/runner.py +++ b/src/openpower/test/runner.py @@ -151,6 +151,7 @@ class TestRunnerBase(FHDLTestCase): xics=False, gpio=False, regreduce=not self.allow_overlap, + core_domain="sync", # no alternative domain svp64=self.svp64, allow_overlap=self.allow_overlap, mmu=self.microwatt_mmu, @@ -181,6 +182,8 @@ class TestRunnerBase(FHDLTestCase): # but Simulation-only fails without it intclk = ClockSignal("coresync") comb += intclk.eq(ClockSignal()) + dbgclk = ClockSignal("dbgsync") + comb += dbgclk.eq(ClockSignal()) # nmigen Simulation - everything runs around this, so it # still has to be created. -- 2.30.2