From b387326dbc6b4bf2452191b6817529133ff362a5 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sat, 7 Jan 2017 17:56:22 -0800 Subject: [PATCH] Make SIP.STIP read-only h/t Ron Minnich See https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/JV-Hj3W5Kw8 --- riscv/processor.cc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index f3764ae..75f4002 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -373,9 +373,10 @@ void processor_t::set_csr(int which, reg_t val) | SSTATUS_XS | SSTATUS_PUM; return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask)); } - case CSR_SIP: - return set_csr(CSR_MIP, - (state.mip & ~state.mideleg) | (val & state.mideleg)); + case CSR_SIP: { + reg_t mask = MIP_SSIP; + return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask)); + } case CSR_SIE: return set_csr(CSR_MIE, (state.mie & ~state.mideleg) | (val & state.mideleg)); -- 2.30.2