From b396dccfff47a5f94457f4b43c16c16da77fcc25 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 29 Mar 2023 15:36:54 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls010.mdwn | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn index ce6b50c29..d8d4886e6 100644 --- a/openpower/sv/rfc/ls010.mdwn +++ b/openpower/sv/rfc/ls010.mdwn @@ -51,7 +51,7 @@ In the Upper Compliancy Levels the size of the GPR and FPR Register files are ex from 32 to 128 entries, and the number of CR Fields expanded from CR0-CR7 to CR0-CR127. Memory access remains exactly the same: the effects of `MSR.LE` remain exactly the same, -affecting as they already do and remain to **only** the Load and Store memory-register +affecting as they already do and remain **only** on the Load and Store memory-register operation byte-order, and having nothing to do with the ordering of the contents of register files or register-register operations. @@ -123,7 +123,7 @@ eight times and pull all eight write-port byte-level lines HIGH. Clearly when el is set to 8-bit the relevant predicate mask bit corresponds directly with one single byte-level write-enable line. It is up to the Hardware Architect to then amortise (merge) elements together into both PredicatedSIMD Pipelines as well as simultaneous non-overlapping -Register File writesto achieve High Performance designs. +Register File writes, to achieve High Performance designs. ## SVP64 encoding features @@ -136,7 +136,7 @@ A number of features need to be compacted into a very small space of only 24 bit * SV Modes including saturation (for Audio, Video and DSP), mapreduce, fail-first and predicate-result mode. -This document focusses specifically on how that fits into available space. The [[svp64/appendix]] explains more of the details, whilst the [[sv/overview]] gives the basics. +Different classes of operations require # Definition of Reserved in this spec. @@ -152,6 +152,12 @@ Unless otherwise stated, reserved values are always all zeros. This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero. Where the standard Power ISA definition is intended the red keyword `RESERVED` is used. +# Definition of "UnVectoriseable" + +Any operation that inherently makes no sense if repeated is termed "UnVectoriseable" +or "UnVectorised". Examples include `sc` or `sync` which have no registers. `mtmsr` is +also classed as UnVectoriseable because there is only one `MSR`. + # Scalar Identity Behaviour SVP64 is designed so that when the prefix is all zeros, and -- 2.30.2