From b3996230909cabd6fa2a56adf095c6943e73019a Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Mon, 7 Aug 2023 16:04:00 -0700 Subject: [PATCH] split out instructions from openpower/isa/fixedlogical.mdwn --- openpower/isa/fixedlogical.mdwn | 572 ++----------------- openpower/isa/fixedlogical/and.mdwn | 14 + openpower/isa/fixedlogical/and_code.mdwn | 1 + openpower/isa/fixedlogical/andc.mdwn | 14 + openpower/isa/fixedlogical/andc_code.mdwn | 1 + openpower/isa/fixedlogical/andi..mdwn | 13 + openpower/isa/fixedlogical/andi._code.mdwn | 1 + openpower/isa/fixedlogical/andis..mdwn | 13 + openpower/isa/fixedlogical/andis._code.mdwn | 1 + openpower/isa/fixedlogical/bpermd.mdwn | 13 + openpower/isa/fixedlogical/bpermd_code.mdwn | 8 + openpower/isa/fixedlogical/cfuged.mdwn | 13 + openpower/isa/fixedlogical/cfuged_code.mdwn | 11 + openpower/isa/fixedlogical/cmpb.mdwn | 13 + openpower/isa/fixedlogical/cmpb_code.mdwn | 5 + openpower/isa/fixedlogical/cntlzd.mdwn | 14 + openpower/isa/fixedlogical/cntlzd_code.mdwn | 6 + openpower/isa/fixedlogical/cntlzdm.mdwn | 13 + openpower/isa/fixedlogical/cntlzdm_code.mdwn | 6 + openpower/isa/fixedlogical/cntlzw.mdwn | 14 + openpower/isa/fixedlogical/cntlzw_code.mdwn | 6 + openpower/isa/fixedlogical/cnttzd.mdwn | 14 + openpower/isa/fixedlogical/cnttzd_code.mdwn | 6 + openpower/isa/fixedlogical/cnttzdm.mdwn | 13 + openpower/isa/fixedlogical/cnttzdm_code.mdwn | 6 + openpower/isa/fixedlogical/cnttzw.mdwn | 14 + openpower/isa/fixedlogical/cnttzw_code.mdwn | 6 + openpower/isa/fixedlogical/eqv.mdwn | 14 + openpower/isa/fixedlogical/eqv_code.mdwn | 1 + openpower/isa/fixedlogical/extsb.mdwn | 14 + openpower/isa/fixedlogical/extsb_code.mdwn | 1 + openpower/isa/fixedlogical/extsh.mdwn | 14 + openpower/isa/fixedlogical/extsh_code.mdwn | 1 + openpower/isa/fixedlogical/extsw.mdwn | 14 + openpower/isa/fixedlogical/extsw_code.mdwn | 1 + openpower/isa/fixedlogical/nand.mdwn | 14 + openpower/isa/fixedlogical/nand_code.mdwn | 1 + openpower/isa/fixedlogical/nor.mdwn | 14 + openpower/isa/fixedlogical/nor_code.mdwn | 1 + openpower/isa/fixedlogical/or.mdwn | 14 + openpower/isa/fixedlogical/or_code.mdwn | 1 + openpower/isa/fixedlogical/orc.mdwn | 14 + openpower/isa/fixedlogical/orc_code.mdwn | 1 + openpower/isa/fixedlogical/ori.mdwn | 13 + openpower/isa/fixedlogical/ori_code.mdwn | 1 + openpower/isa/fixedlogical/oris.mdwn | 13 + openpower/isa/fixedlogical/oris_code.mdwn | 1 + openpower/isa/fixedlogical/pdepd.mdwn | 13 + openpower/isa/fixedlogical/pdepd_code.mdwn | 10 + openpower/isa/fixedlogical/pextd.mdwn | 13 + openpower/isa/fixedlogical/pextd_code.mdwn | 10 + openpower/isa/fixedlogical/popcntb.mdwn | 13 + openpower/isa/fixedlogical/popcntb_code.mdwn | 6 + openpower/isa/fixedlogical/popcntd.mdwn | 13 + openpower/isa/fixedlogical/popcntd_code.mdwn | 5 + openpower/isa/fixedlogical/popcntw.mdwn | 13 + openpower/isa/fixedlogical/popcntw_code.mdwn | 8 + openpower/isa/fixedlogical/prtyd.mdwn | 13 + openpower/isa/fixedlogical/prtyd_code.mdwn | 4 + openpower/isa/fixedlogical/prtyw.mdwn | 13 + openpower/isa/fixedlogical/prtyw_code.mdwn | 8 + openpower/isa/fixedlogical/xor.mdwn | 14 + openpower/isa/fixedlogical/xor_code.mdwn | 1 + openpower/isa/fixedlogical/xori.mdwn | 13 + openpower/isa/fixedlogical/xori_code.mdwn | 1 + openpower/isa/fixedlogical/xoris.mdwn | 13 + openpower/isa/fixedlogical/xoris_code.mdwn | 1 + 67 files changed, 605 insertions(+), 539 deletions(-) create mode 100644 openpower/isa/fixedlogical/and.mdwn create mode 100644 openpower/isa/fixedlogical/and_code.mdwn create mode 100644 openpower/isa/fixedlogical/andc.mdwn create mode 100644 openpower/isa/fixedlogical/andc_code.mdwn create mode 100644 openpower/isa/fixedlogical/andi..mdwn create mode 100644 openpower/isa/fixedlogical/andi._code.mdwn create mode 100644 openpower/isa/fixedlogical/andis..mdwn create mode 100644 openpower/isa/fixedlogical/andis._code.mdwn create mode 100644 openpower/isa/fixedlogical/bpermd.mdwn create mode 100644 openpower/isa/fixedlogical/bpermd_code.mdwn create mode 100644 openpower/isa/fixedlogical/cfuged.mdwn create mode 100644 openpower/isa/fixedlogical/cfuged_code.mdwn create mode 100644 openpower/isa/fixedlogical/cmpb.mdwn create mode 100644 openpower/isa/fixedlogical/cmpb_code.mdwn create mode 100644 openpower/isa/fixedlogical/cntlzd.mdwn create mode 100644 openpower/isa/fixedlogical/cntlzd_code.mdwn create mode 100644 openpower/isa/fixedlogical/cntlzdm.mdwn create mode 100644 openpower/isa/fixedlogical/cntlzdm_code.mdwn create mode 100644 openpower/isa/fixedlogical/cntlzw.mdwn create mode 100644 openpower/isa/fixedlogical/cntlzw_code.mdwn create mode 100644 openpower/isa/fixedlogical/cnttzd.mdwn create mode 100644 openpower/isa/fixedlogical/cnttzd_code.mdwn create mode 100644 openpower/isa/fixedlogical/cnttzdm.mdwn create mode 100644 openpower/isa/fixedlogical/cnttzdm_code.mdwn create mode 100644 openpower/isa/fixedlogical/cnttzw.mdwn create mode 100644 openpower/isa/fixedlogical/cnttzw_code.mdwn create mode 100644 openpower/isa/fixedlogical/eqv.mdwn create mode 100644 openpower/isa/fixedlogical/eqv_code.mdwn create mode 100644 openpower/isa/fixedlogical/extsb.mdwn create mode 100644 openpower/isa/fixedlogical/extsb_code.mdwn create mode 100644 openpower/isa/fixedlogical/extsh.mdwn create mode 100644 openpower/isa/fixedlogical/extsh_code.mdwn create mode 100644 openpower/isa/fixedlogical/extsw.mdwn create mode 100644 openpower/isa/fixedlogical/extsw_code.mdwn create mode 100644 openpower/isa/fixedlogical/nand.mdwn create mode 100644 openpower/isa/fixedlogical/nand_code.mdwn create mode 100644 openpower/isa/fixedlogical/nor.mdwn create mode 100644 openpower/isa/fixedlogical/nor_code.mdwn create mode 100644 openpower/isa/fixedlogical/or.mdwn create mode 100644 openpower/isa/fixedlogical/or_code.mdwn create mode 100644 openpower/isa/fixedlogical/orc.mdwn create mode 100644 openpower/isa/fixedlogical/orc_code.mdwn create mode 100644 openpower/isa/fixedlogical/ori.mdwn create mode 100644 openpower/isa/fixedlogical/ori_code.mdwn create mode 100644 openpower/isa/fixedlogical/oris.mdwn create mode 100644 openpower/isa/fixedlogical/oris_code.mdwn create mode 100644 openpower/isa/fixedlogical/pdepd.mdwn create mode 100644 openpower/isa/fixedlogical/pdepd_code.mdwn create mode 100644 openpower/isa/fixedlogical/pextd.mdwn create mode 100644 openpower/isa/fixedlogical/pextd_code.mdwn create mode 100644 openpower/isa/fixedlogical/popcntb.mdwn create mode 100644 openpower/isa/fixedlogical/popcntb_code.mdwn create mode 100644 openpower/isa/fixedlogical/popcntd.mdwn create mode 100644 openpower/isa/fixedlogical/popcntd_code.mdwn create mode 100644 openpower/isa/fixedlogical/popcntw.mdwn create mode 100644 openpower/isa/fixedlogical/popcntw_code.mdwn create mode 100644 openpower/isa/fixedlogical/prtyd.mdwn create mode 100644 openpower/isa/fixedlogical/prtyd_code.mdwn create mode 100644 openpower/isa/fixedlogical/prtyw.mdwn create mode 100644 openpower/isa/fixedlogical/prtyw_code.mdwn create mode 100644 openpower/isa/fixedlogical/xor.mdwn create mode 100644 openpower/isa/fixedlogical/xor_code.mdwn create mode 100644 openpower/isa/fixedlogical/xori.mdwn create mode 100644 openpower/isa/fixedlogical/xori_code.mdwn create mode 100644 openpower/isa/fixedlogical/xoris.mdwn create mode 100644 openpower/isa/fixedlogical/xoris_code.mdwn diff --git a/openpower/isa/fixedlogical.mdwn b/openpower/isa/fixedlogical.mdwn index 01eeffb1..6b578f17 100644 --- a/openpower/isa/fixedlogical.mdwn +++ b/openpower/isa/fixedlogical.mdwn @@ -10,574 +10,68 @@ -# AND Immediate +[[!inline pagenames="openpower/isa/fixedlogical/andi." raw="yes"]] -D-Form +[[!inline pagenames="openpower/isa/fixedlogical/ori" raw="yes"]] -* andi. RA,RS,UI +[[!inline pagenames="openpower/isa/fixedlogical/andis." raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/fixedlogical/oris" raw="yes"]] - RA <- (RS) & EXTZ(UI) +[[!inline pagenames="openpower/isa/fixedlogical/xoris" raw="yes"]] -Special Registers Altered: +[[!inline pagenames="openpower/isa/fixedlogical/xori" raw="yes"]] - CR0 +[[!inline pagenames="openpower/isa/fixedlogical/and" raw="yes"]] -# OR Immediate +[[!inline pagenames="openpower/isa/fixedlogical/or" raw="yes"]] -D-Form +[[!inline pagenames="openpower/isa/fixedlogical/xor" raw="yes"]] -* ori RA,RS,UI +[[!inline pagenames="openpower/isa/fixedlogical/nand" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/fixedlogical/nor" raw="yes"]] - RA <- (RS) | EXTZ(UI) +[[!inline pagenames="openpower/isa/fixedlogical/eqv" raw="yes"]] -Special Registers Altered: +[[!inline pagenames="openpower/isa/fixedlogical/andc" raw="yes"]] - None +[[!inline pagenames="openpower/isa/fixedlogical/orc" raw="yes"]] -# AND Immediate Shifted +[[!inline pagenames="openpower/isa/fixedlogical/extsb" raw="yes"]] -D-Form +[[!inline pagenames="openpower/isa/fixedlogical/extsh" raw="yes"]] -* andis. RA,RS,UI +[[!inline pagenames="openpower/isa/fixedlogical/cntlzw" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/fixedlogical/cnttzw" raw="yes"]] - RA <- (RS) & EXTZ(UI || [0]*16) +[[!inline pagenames="openpower/isa/fixedlogical/cmpb" raw="yes"]] -Special Registers Altered: +[[!inline pagenames="openpower/isa/fixedlogical/popcntb" raw="yes"]] - CR0 +[[!inline pagenames="openpower/isa/fixedlogical/popcntw" raw="yes"]] -# OR Immediate Shifted +[[!inline pagenames="openpower/isa/fixedlogical/prtyd" raw="yes"]] -D-Form +[[!inline pagenames="openpower/isa/fixedlogical/prtyw" raw="yes"]] -* oris RA,RS,UI +[[!inline pagenames="openpower/isa/fixedlogical/extsw" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/fixedlogical/popcntd" raw="yes"]] - RA <- (RS) | EXTZ(UI || [0]*16) +[[!inline pagenames="openpower/isa/fixedlogical/cntlzd" raw="yes"]] -Special Registers Altered: +[[!inline pagenames="openpower/isa/fixedlogical/cnttzd" raw="yes"]] - None +[[!inline pagenames="openpower/isa/fixedlogical/cntlzdm" raw="yes"]] -# XOR Immediate Shifted +[[!inline pagenames="openpower/isa/fixedlogical/cnttzdm" raw="yes"]] -D-Form +[[!inline pagenames="openpower/isa/fixedlogical/bpermd" raw="yes"]] -* xoris RA,RS,UI +[[!inline pagenames="openpower/isa/fixedlogical/cfuged" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/fixedlogical/pextd" raw="yes"]] - RA <- (RS) ^ EXTZ(UI || [0]*16) - -Special Registers Altered: - - None - -# XOR Immediate - -D-Form - -* xori RA,RS,UI - -Pseudo-code: - - RA <- (RS) ^ EXTZ(UI) - -Special Registers Altered: - - None - -# AND - -X-Form - -* and RA,RS,RB (Rc=0) -* and. RA,RS,RB (Rc=1) - -Pseudo-code: - - RA <- (RS) & (RB) - -Special Registers Altered: - - CR0 (if Rc=1) - -# OR - -X-Form - -* or RA,RS,RB (Rc=0) -* or. RA,RS,RB (Rc=1) - -Pseudo-code: - - RA <- (RS) | (RB) - -Special Registers Altered: - - CR0 (if Rc=1) - -# XOR - -X-Form - -* xor RA,RS,RB (Rc=0) -* xor. RA,RS,RB (Rc=1) - -Pseudo-code: - - RA <- (RS) ^ (RB) - -Special Registers Altered: - - CR0 (if Rc=1) - -# NAND - -X-Form - -* nand RA,RS,RB (Rc=0) -* nand. RA,RS,RB (Rc=1) - -Pseudo-code: - - RA <- ¬((RS) & (RB)) - -Special Registers Altered: - - CR0 (if Rc=1) - -# NOR - -X-Form - -* nor RA,RS,RB (Rc=0) -* nor. RA,RS,RB (Rc=1) - -Pseudo-code: - - RA <- ¬((RS) | (RB)) - -Special Registers Altered: - - CR0 (if Rc=1) - -# Equivalent - -X-Form - -* eqv RA,RS,RB (Rc=0) -* eqv. RA,RS,RB (Rc=1) - -Pseudo-code: - - RA <- ¬((RS) ^ (RB)) - -Special Registers Altered: - - CR0 (if Rc=1) - -# AND with Complement - -X-Form - -* andc RA,RS,RB (Rc=0) -* andc. RA,RS,RB (Rc=1) - -Pseudo-code: - - RA <- (RS) & ¬(RB) - -Special Registers Altered: - - CR0 (if Rc=1) - -# OR with Complement - -X-Form - -* orc RA,RS,RB (Rc=0) -* orc. RA,RS,RB (Rc=1) - -Pseudo-code: - - RA <- (RS) | ¬(RB) - -Special Registers Altered: - - CR0 (if Rc=1) - -# Extend Sign Byte - -X-Form - -* extsb RA,RS (Rc=0) -* extsb. RA,RS (Rc=1) - -Pseudo-code: - - RA <- EXTSXL(RS, XLEN/8) - -Special Registers Altered: - - CR0 (if Rc=1) - -# Extend Sign Halfword - -X-Form - -* extsh RA,RS (Rc=0) -* extsh. RA,RS (Rc=1) - -Pseudo-code: - - RA <- EXTSXL(RS, XLEN/4) - -Special Registers Altered: - - CR0 (if Rc=1) - -# Count Leading Zeros Word - -X-Form - -* cntlzw RA,RS (Rc=0) -* cntlzw. RA,RS (Rc=1) - -Pseudo-code: - - n <- (XLEN/2) - do while n < XLEN - if (RS)[n] = 1 then - leave - n <- n + 1 - RA <- n - (XLEN/2) - -Special Registers Altered: - - CR0 (if Rc=1) - -# Count Trailing Zeros Word - -X-Form - -* cnttzw RA,RS (Rc=0) -* cnttzw. RA,RS (Rc=1) - -Pseudo-code: - - n <- 0 - do while n < XLEN/2 - if (RS)[XLEN-1-n] = 0b1 then - leave - n <- n + 1 - RA <- EXTZ(n) - -Special Registers Altered: - - CR0 (if Rc=1) - -# Compare Bytes - -X-Form - -* cmpb RA,RS,RB - -Pseudo-code: - - do n = 0 to ((XLEN/8)-1) - if RS[8*n:8* n+7] = (RB)[8*n:8*n+7] then - RA[8*n:8* n+7] <- [1]*8 - else - RA[8*n:8* n+7] <- [0]*8 - -Special Registers Altered: - - None - -# Population Count Bytes - -X-Form - -* popcntb RA,RS - -Pseudo-code: - - do i = 0 to ((XLEN/8)-1) - n <- 0 - do j = 0 to 7 - if (RS)[(i*8)+j] = 1 then - n <- n+1 - RA[(i*8):(i*8)+7] <- n - -Special Registers Altered: - - None - -# Population Count Words - -X-Form - -* popcntw RA,RS - -Pseudo-code: - - e <- (XLEN/2)-1 - do i = 0 to 1 - s <- i*XLEN/2 - n <- 0 - do j = 0 to e - if (RS)[s+j] = 1 then - n <- n+1 - RA[s:s+e] <- n - -Special Registers Altered: - - None - -# Parity Doubleword - -X-Form - -* prtyd RA,RS - -Pseudo-code: - - s <- 0 - do i = 0 to ((XLEN/8)-1) - s <- s ^ (RS)[i*8+7] - RA <- [0] * (XLEN-1) || s - -Special Registers Altered: - - None - -# Parity Word - -X-Form - -* prtyw RA,RS - -Pseudo-code: - - s <- 0 - t <- 0 - do i = 0 to ((XLEN/8/2)-1) - s <- s ^ (RS)[i*8+7] - do i = 4 to ((XLEN/8)-1) - t <- t ^ (RS)[i*8+7] - RA[0:(XLEN/2)-1] <- [0]*((XLEN/2)-1) || s - RA[XLEN/2:XLEN-1] <- [0]*((XLEN/2)-1) || t - -Special Registers Altered: - - None - -# Extend Sign Word - -X-Form - -* extsw RA,RS (Rc=0) -* extsw. RA,RS (Rc=1) - -Pseudo-code: - - RA <- EXTSXL(RS, XLEN/2) - -Special Registers Altered: - - CR0 (if Rc=1) - -# Population Count Doubleword - -X-Form - -* popcntd RA,RS - -Pseudo-code: - - n <- 0 - do i = 0 to (XLEN-1) - if (RS)[i] = 1 then - n <- n+1 - RA <- n - -Special Registers Altered: - - None - -# Count Leading Zeros Doubleword - -X-Form - -* cntlzd RA,RS (Rc=0) -* cntlzd. RA,RS (Rc=1) - -Pseudo-code: - - n <- 0 - do while n < XLEN - if (RS)[n] = 1 then - leave - n <- n + 1 - RA <- n - -Special Registers Altered: - - CR0 (if Rc=1) - -# Count Trailing Zeros Doubleword - -X-Form - -* cnttzd RA,RS (Rc=0) -* cnttzd. RA,RS (Rc=1) - -Pseudo-code: - - n <- 0 - do while n < XLEN - if (RS)[XLEN-1-n] = 0b1 then - leave - n <- n + 1 - RA <- EXTZ(n) - -Special Registers Altered: - - CR0 (if Rc=1) - -# Count Leading Zeros Doubleword under bit Mask - -X-Form - -* cntlzdm RA,RS,RB - -Pseudo-code: - - count <- 0 - do i = 0 to 63 - if (RB)[i] = 1 then - if (RS)[i] = 1 then leave - count <- count + 1 - RA <- EXTZ64(count) - -Special Registers Altered: - - None - -# Count Trailing Zeros Doubleword under bit Mask - -X-Form - -* cnttzdm RA,RS,RB - -Pseudo-code: - - count <- 0 - do i = 0 to 63 - if (RB)[63-i] = 1 then - if (RS)[63-i] = 1 then leave - count <- count + 1 - RA <- EXTZ64(count) - -Special Registers Altered: - - None - -# Bit Permute Doubleword - -X-Form - -* bpermd RA,RS,RB - -Pseudo-code: - - perm <- [0] * (XLEN/8) - for i = 0 to ((XLEN/8)-1) - index <- (RS)[8*i:8*i+7] - if index