From b3acc3f6b80a7c80ea10ac12227b1c3c28719c12 Mon Sep 17 00:00:00 2001
From: Andrey Miroshnikov <andrey@technepisteme.xyz>
Date: Wed, 22 Jun 2022 14:07:06 +0100
Subject: [PATCH] Added cprop to caller, enums, svp64

---
 src/openpower/decoder/isa/caller.py  | 5 +++++
 src/openpower/decoder/power_enums.py | 1 +
 src/openpower/sv/trans/svp64.py      | 6 +++++-
 3 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 7b8224e4..275be81f 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1294,6 +1294,11 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
             illegal = False
             ins_name = asmop
 
+        # and anything cprop
+        if asmop.startswith('cprop'):
+            illegal = False
+            ins_name = asmop
+
         # and anything ternlog
         if asmop.startswith('ternlog'):
             illegal = False
diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 4587c6ad..995806c8 100644
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -269,6 +269,7 @@ _insns = [
     "cdtbcd",
     "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
     "cntlzd", "cntlzw", "cnttzd", "cnttzw",
+    "cprop", # AV bitmanip
     "crand", "crandc", "creqv",
     "crnand", "crnor", "cror", "crorc", "crxor",
     "darn",
diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index f7bed852..d5c7842f 100644
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -443,7 +443,8 @@ class SVP64Asm:
 
         # and avgadd, absdu, absdacu, absdacs
         # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
-        if opcode in ['avgadd', 'absdu', 'absds', 'absdacu', 'absdacs']:
+        if opcode in ['avgadd', 'absdu', 'absds', 'absdacu', 'absdacs',
+                      'cprop']:
             if opcode[:5] == 'absdu':
                 XO = 0b1011110110
             elif opcode[:5] == 'absds':
@@ -454,6 +455,8 @@ class SVP64Asm:
                 XO = 0b1111110110
             elif opcode[:7] == 'absdacs':
                 XO = 0b0111110110
+            elif opcode[:7] == 'cprop':
+                XO = 0b0110001110
             fields = list(map(int, fields))
             insn = 22 << (31-5)  # opcode 22, bits 0-5
             insn |= fields[0] << (31-10)  # RT       , bits 6-10
@@ -1344,6 +1347,7 @@ if __name__ == '__main__':
         'absds 3,12,5',
         'absdacu 3,12,5',
         'absdacs 3,12,5',
+        'cprop 3,12,5',
     ]
     isa = SVP64Asm(lst, macros=macros)
     log("list", list(isa))
-- 
2.30.2