From b3c1449e498574e7637e1ff7fcae9f6f85132fab Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 15 Apr 2022 18:32:56 +0100 Subject: [PATCH] checking simulation of Async DDR3 --- simsoc.ys | 14 ++++++++++++-- src/ecp5_crg.py | 6 +++--- src/ls2.py | 4 +++- 3 files changed, 18 insertions(+), 6 deletions(-) diff --git a/simsoc.ys b/simsoc.ys index e5e237a..a4adcef 100644 --- a/simsoc.ys +++ b/simsoc.ys @@ -3,7 +3,13 @@ # models because apparently they're good to go, already (icarus is a lot # stricter than verilator, hence the munging below) +# peripheral fabric read_ilang build_simsoc/top.il + +# main core (any core, it's all good) +read_verilog ./external_core_top.v + +# UART 16550 read_verilog ../uart16550/rtl/verilog/raminfr.v read_verilog ../uart16550/rtl/verilog/uart_defines.v read_verilog ../uart16550/rtl/verilog/uart_rfifo.v @@ -16,8 +22,14 @@ read_verilog ../uart16550/rtl/verilog/uart_transmitter.v read_verilog ../uart16550/rtl/verilog/uart_receiver.v read_verilog ../uart16550/rtl/verilog/uart_tfifo.v read_verilog ../uart16550/rtl/verilog/uart_wb.v + +# Tercel QSPI read_verilog ../tercel-qspi/tercel/phy.v read_verilog ../tercel-qspi/tercel/wishbone_spi_master.v + +# WB Async Bridge +read_verilog ../verilog-wishbone/rtl/wb_async_reg.v + # errors in the ethmac rtl, comment out for now #read_verilog ../ethmac/rtl/verilog/eth_clockgen.v #read_verilog ../ethmac/rtl/verilog/eth_cop.v @@ -47,8 +59,6 @@ read_verilog ../tercel-qspi/tercel/wishbone_spi_master.v #read_verilog ../ethmac/rtl/verilog/eth_wishbone.v #read_verilog ../ethmac/rtl/verilog/timescale.v -read_verilog ./external_core_top.v - # stop yosys deleting stuff setattr -mod -set keep 1 uart_transmitter setattr -mod -set keep 1 uart_receiver diff --git a/src/ecp5_crg.py b/src/ecp5_crg.py index bd91df1..980e62d 100644 --- a/src/ecp5_crg.py +++ b/src/ecp5_crg.py @@ -282,9 +282,6 @@ class ECP5CRG(Elaboratable): # a CLKESYNCB (which is set to no-stop at the moment) if self.dram_clk_freq is not None: self.phase2_domain(m, pll, "dramsync", self.dram_clk_freq, True) - # resets for the dram domains - m.d.comb += ResetSignal("dramsync2x").eq(reset_ok) - m.d.comb += ResetSignal("dramsync").eq(reset_ok) else: # alias dramsync and dramsync2x to sync and sync2x cd_dramsync = ClockDomain("dramsync", local=False) @@ -294,6 +291,9 @@ class ECP5CRG(Elaboratable): cd_dramsync2x = ClockDomain("dramsync2x", local=False) m.domains += cd_dramsync2x m.d.comb += ClockSignal("dramsync2x").eq(ClockSignal("sync2x")) + # resets for the dram domains + m.d.comb += ResetSignal("dramsync2x").eq(reset_ok) + m.d.comb += ResetSignal("dramsync").eq(reset_ok) # create 25 mhz "init" clock, straight (no 2x phase stuff) cd_init = ClockDomain("init", local=False) diff --git a/src/ls2.py b/src/ls2.py index f7586cf..4dae4a9 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -852,7 +852,8 @@ def build_platform(fpga, firmware): clk_freq = 100e6 dram_clk_freq = clk_freq if fpga == 'isim': - clk_freq = 55e6 # below 50 mhz, stops DRAM being enabled + clk_freq = 50e6 # below 50 mhz, stops DRAM being enabled + dram_clk_freq = 100e6 if fpga == 'versa_ecp5': clk_freq = 50e6 # crank right down to test hyperram #dram_clk_freq = 100e6 @@ -893,6 +894,7 @@ def build_platform(fpga, firmware): "ba":4, "clk_en":4, "odt":4, "ras":4, "cas":4, "we":4, "cs": 4}) + print ("ddr pins", ddr_pins) # Get SPI resource pins spi_0_pins = None -- 2.30.2