From b3d3ce90ac56e1d6b708c503cd37a1739b591428 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Sun, 23 Aug 2020 16:04:13 -0400 Subject: [PATCH] Add copyright to files in fu/ that I was the primary author on --- src/soc/fu/alu/main_stage.py | 2 ++ src/soc/fu/branch/main_stage.py | 1 + src/soc/fu/cr/main_stage.py | 1 + src/soc/fu/logical/main_stage.py | 1 + src/soc/fu/shift_rot/main_stage.py | 1 + src/soc/fu/shift_rot/maskgen.py | 1 + 6 files changed, 7 insertions(+) diff --git a/src/soc/fu/alu/main_stage.py b/src/soc/fu/alu/main_stage.py index b2d2279c..16950629 100644 --- a/src/soc/fu/alu/main_stage.py +++ b/src/soc/fu/alu/main_stage.py @@ -3,6 +3,8 @@ # as well as carry and overflow generation. This module # however should not gate the carry or overflow, that's up to the # output stage + +# Copyright (C) 2020 Michael Nolan from nmigen import (Module, Signal, Cat, Repl, Mux, Const) from nmutil.pipemodbase import PipeModBase from nmutil.extend import exts diff --git a/src/soc/fu/branch/main_stage.py b/src/soc/fu/branch/main_stage.py index 39631afd..8a1b5f0b 100644 --- a/src/soc/fu/branch/main_stage.py +++ b/src/soc/fu/branch/main_stage.py @@ -23,6 +23,7 @@ Links: * https://bugs.libre-soc.org/show_bug.cgi?id=335 * https://libre-soc.org/openpower/isa/branch/ """ +# Copyright (C) 2020 Michael Nolan from nmigen import (Module, Signal, Cat, Mux, Const, Array) from nmutil.pipemodbase import PipeModBase diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py index 27aa6670..36f587eb 100644 --- a/src/soc/fu/cr/main_stage.py +++ b/src/soc/fu/cr/main_stage.py @@ -8,6 +8,7 @@ # own "Register File" (indexed by bt, ba and bb), # exactly how INT regs are done (by RA, RB, RS and RT) # however we are pushed for time so do it as *one* register. +# Copyright (C) 2020 Michael Nolan from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array) from nmutil.pipemodbase import PipeModBase diff --git a/src/soc/fu/logical/main_stage.py b/src/soc/fu/logical/main_stage.py index ea102358..d6ae4a2f 100644 --- a/src/soc/fu/logical/main_stage.py +++ b/src/soc/fu/logical/main_stage.py @@ -5,6 +5,7 @@ # This module however should not gate the carry or overflow, that's up # to the output stage +# Copyright (C) 2020 Michael Nolan from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array) from nmutil.pipemodbase import PipeModBase from nmutil.clz import CLZ diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py index 0ab4c460..7d9dad09 100644 --- a/src/soc/fu/shift_rot/main_stage.py +++ b/src/soc/fu/shift_rot/main_stage.py @@ -2,6 +2,7 @@ # instructions, as well as carry and overflow generation. This module # however should not gate the carry or overflow, that's up to the # output stage +# Copyright (C) 2020 Michael Nolan from nmigen import (Module, Signal, Cat, Repl, Mux, Const) from nmutil.pipemodbase import PipeModBase from soc.fu.logical.pipe_data import LogicalOutputData diff --git a/src/soc/fu/shift_rot/maskgen.py b/src/soc/fu/shift_rot/maskgen.py index 89246e0b..03072110 100644 --- a/src/soc/fu/shift_rot/maskgen.py +++ b/src/soc/fu/shift_rot/maskgen.py @@ -1,5 +1,6 @@ from nmigen import (Elaboratable, Signal, Module) import math +# Copyright (C) 2020 Michael Nolan class MaskGen(Elaboratable): """MaskGen - create a diff mask -- 2.30.2