From b3da4ff862db27f4866e0bf08d796aebfa36b86c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 22 Oct 2020 18:13:57 +0100 Subject: [PATCH] Handle case with zero IO cells for boundary scan. --- c4m/nmigen/jtag/tap.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/c4m/nmigen/jtag/tap.py b/c4m/nmigen/jtag/tap.py index 13a78b2..9e260c3 100755 --- a/c4m/nmigen/jtag/tap.py +++ b/c4m/nmigen/jtag/tap.py @@ -399,8 +399,9 @@ class TAP(Elaboratable): m.d.comb += tdo.eq(irblock.tdo) with m.Elif(select_id): m.d.comb += tdo.eq(idblock.tdo) - with m.Elif(select_io): - m.d.comb += tdo.eq(io_tdo) + if io_tdo is not None: + with m.Elif(select_io): + m.d.comb += tdo.eq(io_tdo) # shiftregs block self._elaborate_shiftregs( @@ -438,6 +439,8 @@ class TAP(Elaboratable): IOType.InTriOut: 3, } length = sum(connlength[conn._iotype] for conn in self._ios) + if length == 0: + return None io_sr = Signal(length) io_bd = Signal(length) @@ -499,7 +502,6 @@ class TAP(Elaboratable): return io_sr[-1] - def add_shiftreg(self, *, ircode, length, domain="sync", name=None, src_loc_at=0): """Add a shift register to the JTAG interface -- 2.30.2