From b3e4658b1621643b92fb6b7a2f864a99347a4441 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Fri, 8 May 2020 10:40:06 -0400 Subject: [PATCH] Separate out ALU Input record from alu_hier.py --- src/soc/alu/alu_input_record.py | 82 +++++++++++++++++++++++++++++++++ src/soc/experiment/alu_hier.py | 79 +------------------------------ 2 files changed, 84 insertions(+), 77 deletions(-) create mode 100644 src/soc/alu/alu_input_record.py diff --git a/src/soc/alu/alu_input_record.py b/src/soc/alu/alu_input_record.py new file mode 100644 index 00000000..0ce965b5 --- /dev/null +++ b/src/soc/alu/alu_input_record.py @@ -0,0 +1,82 @@ +from nmigen.hdl.rec import Record, Layout + +from soc.decoder.power_enums import InternalOp, Function, CryIn + + +class CompALUOpSubset(Record): + """CompALUOpSubset + + a copy of the relevant subset information from Decode2Execute1Type + needed for ALU operations. use with eq_from_execute1 (below) to + grab subsets. + """ + def __init__(self, name=None): + layout = (('insn_type', InternalOp), + ('fn_unit', Function), + ('nia', 64), + ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))), + #'cr = Signal(32, reset_less=True) # NO: this is from the CR SPR + #'xerc = XerBits() # NO: this is from the XER SPR + ('lk', 1), + ('rc', Layout((("rc", 1), ("rc_ok", 1)))), + ('oe', Layout((("oe", 1), ("oe_ok", 1)))), + ('invert_a', 1), + ('invert_out', 1), + ('input_carry', CryIn), + ('output_carry', 1), + ('input_cr', 1), + ('output_cr', 1), + ('is_32bit', 1), + ('is_signed', 1), + ('data_len', 4), # TODO: should be in separate CompLDSTSubset + ('byte_reverse', 1), + ('sign_extend', 1)) + + Record.__init__(self, Layout(layout), name=name) + + # grrr. Record does not have kwargs + self.insn_type.reset_less = True + self.fn_unit.reset_less = True + self.nia.reset_less = True + #self.cr = Signal(32, reset_less = True + #self.xerc = XerBits( + self.lk.reset_less = True + self.invert_a.reset_less = True + self.invert_out.reset_less = True + self.input_carry.reset_less = True + self.output_carry.reset_less = True + self.input_cr.reset_less = True + self.output_cr.reset_less = True + self.is_32bit.reset_less = True + self.is_signed.reset_less = True + self.data_len.reset_less = True + self.byte_reverse.reset_less = True + self.sign_extend.reset_less = True + + def eq_from_execute1(self, other): + """ use this to copy in from Decode2Execute1Type + """ + res = [] + for fname, sig in self.fields.items(): + eqfrom = other.fields[fname] + res.append(sig.eq(eqfrom)) + return res + + def ports(self): + return [self.insn_type, + self.nia, + #self.cr, + #self.xerc, + self.lk, + self.invert_a, + self.invert_out, + self.input_carry, + self.output_carry, + self.input_cr, + self.output_cr, + self.is_32bit, + self.is_signed, + self.data_len, + self.byte_reverse, + self.sign_extend, + ] diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py index 0021c079..2a10ed15 100644 --- a/src/soc/experiment/alu_hier.py +++ b/src/soc/experiment/alu_hier.py @@ -17,86 +17,11 @@ from nmigen.compat.sim import run_simulation from soc.decoder.power_enums import InternalOp, Function, CryIn -import operator +from soc.alu.alu_input_record import CompALUOpSubset +import operator -class CompALUOpSubset(Record): - """CompALUOpSubset - - a copy of the relevant subset information from Decode2Execute1Type - needed for ALU operations. use with eq_from_execute1 (below) to - grab subsets. - """ - def __init__(self, name=None): - layout = (('insn_type', InternalOp), - ('fn_unit', Function), - ('nia', 64), - ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))), - #'cr = Signal(32, reset_less=True) # NO: this is from the CR SPR - #'xerc = XerBits() # NO: this is from the XER SPR - ('lk', 1), - ('rc', Layout((("rc", 1), ("rc_ok", 1)))), - ('oe', Layout((("oe", 1), ("oe_ok", 1)))), - ('invert_a', 1), - ('invert_out', 1), - ('input_carry', CryIn), - ('output_carry', 1), - ('input_cr', 1), - ('output_cr', 1), - ('is_32bit', 1), - ('is_signed', 1), - ('data_len', 4), # TODO: should be in separate CompLDSTSubset - ('byte_reverse', 1), - ('sign_extend', 1)) - - Record.__init__(self, Layout(layout), name=name) - - # grrr. Record does not have kwargs - self.insn_type.reset_less = True - self.fn_unit.reset_less = True - self.nia.reset_less = True - #self.cr = Signal(32, reset_less = True - #self.xerc = XerBits( - self.lk.reset_less = True - self.invert_a.reset_less = True - self.invert_out.reset_less = True - self.input_carry.reset_less = True - self.output_carry.reset_less = True - self.input_cr.reset_less = True - self.output_cr.reset_less = True - self.is_32bit.reset_less = True - self.is_signed.reset_less = True - self.data_len.reset_less = True - self.byte_reverse.reset_less = True - self.sign_extend.reset_less = True - - def eq_from_execute1(self, other): - """ use this to copy in from Decode2Execute1Type - """ - res = [] - for fname, sig in self.fields.items(): - eqfrom = other.fields[fname] - res.append(sig.eq(eqfrom)) - return res - def ports(self): - return [self.insn_type, - self.nia, - #self.cr, - #self.xerc, - self.lk, - self.invert_a, - self.invert_out, - self.input_carry, - self.output_carry, - self.input_cr, - self.output_cr, - self.is_32bit, - self.is_signed, - self.data_len, - self.byte_reverse, - self.sign_extend, - ] class Adder(Elaboratable): -- 2.30.2