From b3f08b5424f581092b375c335c722fced25fb40e Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Fri, 22 Apr 2016 14:32:48 -0700 Subject: [PATCH] i965/blorp: Turn brw_blorp_params into a C-style struct Reviewed-by: Topi Pohjolainen Reviewed-by: Matt Turner --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 33 +++++---------- src/mesa/drivers/dri/i965/brw_blorp.h | 41 +++++++++---------- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 3 +- src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 6 ++- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 40 +++++++++--------- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 14 +++---- src/mesa/drivers/dri/i965/gen8_blorp.cpp | 14 +++---- 7 files changed, 71 insertions(+), 80 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index 85075f847d6..3a43762116d 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp @@ -134,27 +134,15 @@ brw_blorp_compute_tile_offsets(const struct brw_blorp_surface_info *info, } -brw_blorp_params::brw_blorp_params() - : x0(0), - y0(0), - x1(0), - y1(0), - depth_format(0), - hiz_op(GEN6_HIZ_OP_NONE), - fast_clear_op(0), - num_varyings(0), - num_draw_buffers(1), - num_layers(1), - wm_prog_kernel(0), - wm_prog_data(NULL) +void +brw_blorp_params_init(struct brw_blorp_params *params) { - memset(&src, 0, sizeof(src)); - memset(&dst, 0, sizeof(dst)); - memset(&depth, 0, sizeof(depth)); - color_write_disable[0] = false; - color_write_disable[1] = false; - color_write_disable[2] = false; - color_write_disable[3] = false; + memset(params, 0, sizeof(*params)); + params->hiz_op = GEN6_HIZ_OP_NONE; + params->fast_clear_op = 0; + params->num_varyings = 0; + params->num_draw_buffers = 1; + params->num_layers = 1; } extern "C" { @@ -201,7 +189,7 @@ intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, } /* extern "C" */ void -brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params) +brw_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params) { struct gl_context *ctx = &brw->ctx; const uint32_t estimated_max_batch_usage = brw->gen >= 8 ? 1800 : 1500; @@ -290,7 +278,8 @@ void gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, unsigned int level, unsigned int layer, enum gen6_hiz_op op) { - brw_blorp_params params; + struct brw_blorp_params params; + brw_blorp_params_init(¶ms); params.hiz_op = op; diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h index b901de31c87..25c6179785a 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.h +++ b/src/mesa/drivers/dri/i965/brw_blorp.h @@ -217,11 +217,8 @@ struct brw_blorp_prog_data bool persample_msaa_dispatch; }; -class brw_blorp_params +struct brw_blorp_params { -public: - brw_blorp_params(); - uint32_t x0; uint32_t y0; uint32_t x1; @@ -233,17 +230,19 @@ public: enum gen6_hiz_op hiz_op; unsigned fast_clear_op; bool color_write_disable[4]; - brw_blorp_wm_push_constants wm_push_consts; - const unsigned num_varyings; - const unsigned num_draw_buffers; - const unsigned num_layers; + struct brw_blorp_wm_push_constants wm_push_consts; + unsigned num_varyings; + unsigned num_draw_buffers; + unsigned num_layers; uint32_t wm_prog_kernel; struct brw_blorp_prog_data *wm_prog_data; }; +void +brw_blorp_params_init(struct brw_blorp_params *params); void -brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params); +brw_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params); void gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, @@ -251,14 +250,14 @@ gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, void gen6_blorp_exec(struct brw_context *brw, - const brw_blorp_params *params); + const struct brw_blorp_params *params); void gen7_blorp_exec(struct brw_context *brw, - const brw_blorp_params *params); + const struct brw_blorp_params *params); void -gen8_blorp_exec(struct brw_context *brw, const brw_blorp_params *params); +gen8_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params); struct brw_blorp_blit_prog_key { @@ -351,22 +350,22 @@ gen6_blorp_init(struct brw_context *brw); void gen6_blorp_emit_vertices(struct brw_context *brw, - const brw_blorp_params *params); + const struct brw_blorp_params *params); uint32_t gen6_blorp_emit_blend_state(struct brw_context *brw, - const brw_blorp_params *params); + const struct brw_blorp_params *params); uint32_t gen6_blorp_emit_cc_state(struct brw_context *brw); uint32_t gen6_blorp_emit_wm_constants(struct brw_context *brw, - const brw_blorp_params *params); + const struct brw_blorp_params *params); void gen6_blorp_emit_vs_disable(struct brw_context *brw, - const brw_blorp_params *params); + const struct brw_blorp_params *params); uint32_t gen6_blorp_emit_binding_table(struct brw_context *brw, @@ -375,18 +374,18 @@ gen6_blorp_emit_binding_table(struct brw_context *brw, uint32_t gen6_blorp_emit_depth_stencil_state(struct brw_context *brw, - const brw_blorp_params *params); + const struct brw_blorp_params *params); void gen6_blorp_emit_gs_disable(struct brw_context *brw, - const brw_blorp_params *params); + const struct brw_blorp_params *params); void gen6_blorp_emit_clip_disable(struct brw_context *brw); void gen6_blorp_emit_drawing_rectangle(struct brw_context *brw, - const brw_blorp_params *params); + const struct brw_blorp_params *params); uint32_t gen6_blorp_emit_sampler_state(struct brw_context *brw, @@ -419,7 +418,7 @@ gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw, void gen7_blorp_emit_clear_params(struct brw_context *brw, - const brw_blorp_params *params); + const struct brw_blorp_params *params); void gen7_blorp_emit_constant_ps(struct brw_context *brw, @@ -430,7 +429,7 @@ gen7_blorp_emit_constant_ps_disable(struct brw_context *brw); void gen7_blorp_emit_primitive(struct brw_context *brw, - const brw_blorp_params *params); + const struct brw_blorp_params *params); /** \} */ diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp index 177739065e3..ab2ceecde41 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp @@ -1896,7 +1896,8 @@ brw_blorp_blit_miptrees(struct brw_context *brw, if (!encode_srgb && _mesa_get_format_color_encoding(dst_format) == GL_SRGB) dst_format = _mesa_get_srgb_format_linear(dst_format); - brw_blorp_params params; + struct brw_blorp_params params; + brw_blorp_params_init(¶ms); brw_blorp_surface_info_init(brw, ¶ms.src, src_mt, src_level, src_layer, src_format, false); diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp index f64b7138cf5..ed537bab295 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp @@ -232,7 +232,8 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb, struct intel_renderbuffer *irb = intel_renderbuffer(rb); mesa_format format = irb->mt->format; - brw_blorp_params params; + struct brw_blorp_params params; + brw_blorp_params_init(¶ms); if (!encode_srgb && _mesa_get_format_color_encoding(format) == GL_SRGB) format = _mesa_get_srgb_format_linear(format); @@ -400,7 +401,8 @@ brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt) const mesa_format format = _mesa_get_srgb_format_linear(mt->format); - brw_blorp_params params; + struct brw_blorp_params params; + brw_blorp_params_init(¶ms); brw_blorp_surface_info_init(brw, ¶ms.dst, mt, 0 /* level */, 0 /* layer */, format, true); diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index 1f4104b9018..5498070c31d 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -79,7 +79,7 @@ gen6_blorp_emit_vertex_buffer_state(struct brw_context *brw, void gen6_blorp_emit_vertices(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { uint32_t vertex_offset; @@ -188,7 +188,7 @@ gen6_blorp_emit_vertices(struct brw_context *brw, */ static void gen6_blorp_emit_urb_config(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { BEGIN_BATCH(3); OUT_BATCH(_3DSTATE_URB << 16 | (3 - 2)); @@ -201,7 +201,7 @@ gen6_blorp_emit_urb_config(struct brw_context *brw, /* BLEND_STATE */ uint32_t gen6_blorp_emit_blend_state(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { uint32_t cc_blend_state_offset; @@ -252,7 +252,7 @@ gen6_blorp_emit_cc_state(struct brw_context *brw) */ uint32_t gen6_blorp_emit_depth_stencil_state(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { uint32_t depthstencil_offset; @@ -287,7 +287,7 @@ gen6_blorp_emit_depth_stencil_state(struct brw_context *brw, */ static void gen6_blorp_emit_cc_state_pointers(struct brw_context *brw, - const brw_blorp_params *params, + const struct brw_blorp_params *params, uint32_t cc_blend_state_offset, uint32_t depthstencil_offset, uint32_t cc_state_offset) @@ -304,7 +304,7 @@ gen6_blorp_emit_cc_state_pointers(struct brw_context *brw, /* WM push constants */ uint32_t gen6_blorp_emit_wm_constants(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { uint32_t wm_push_const_offset; @@ -323,7 +323,7 @@ gen6_blorp_emit_wm_constants(struct brw_context *brw, */ static uint32_t gen6_blorp_emit_surface_state(struct brw_context *brw, - const brw_blorp_params *params, + const struct brw_blorp_params *params, const struct brw_blorp_surface_info *surface, uint32_t read_domains, uint32_t write_domain) { @@ -484,7 +484,7 @@ gen6_blorp_emit_sampler_state_pointers(struct brw_context *brw, */ void gen6_blorp_emit_vs_disable(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State, * 3DSTATE_VS, Dword 5.0 "VS Function Enable": @@ -523,7 +523,7 @@ gen6_blorp_emit_vs_disable(struct brw_context *brw, */ void gen6_blorp_emit_gs_disable(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { /* Disable all the constant buffers. */ BEGIN_BATCH(5); @@ -593,7 +593,7 @@ gen6_blorp_emit_clip_disable(struct brw_context *brw) */ static void gen6_blorp_emit_sf_config(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { BEGIN_BATCH(20); OUT_BATCH(_3DSTATE_SF << 16 | (20 - 2)); @@ -614,7 +614,7 @@ gen6_blorp_emit_sf_config(struct brw_context *brw, */ static void gen6_blorp_emit_wm_config(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { const struct brw_blorp_prog_data *prog_data = params->wm_prog_data; uint32_t dw2, dw4, dw5, dw6; @@ -687,7 +687,7 @@ gen6_blorp_emit_wm_config(struct brw_context *brw, static void gen6_blorp_emit_constant_ps(struct brw_context *brw, - const brw_blorp_params *params, + const struct brw_blorp_params *params, uint32_t wm_push_const_offset) { /* Make sure the push constants fill an exact integer number of @@ -712,7 +712,7 @@ gen6_blorp_emit_constant_ps(struct brw_context *brw, static void gen6_blorp_emit_constant_ps_disable(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { /* Disable the push constant buffers. */ BEGIN_BATCH(5); @@ -744,7 +744,7 @@ gen6_blorp_emit_binding_table_pointers(struct brw_context *brw, static void gen6_blorp_emit_depth_stencil_config(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { uint32_t surfwidth, surfheight; uint32_t surftype; @@ -859,7 +859,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw, static void gen6_blorp_emit_depth_disable(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { brw_emit_depth_stall_flushes(brw); @@ -896,7 +896,7 @@ gen6_blorp_emit_depth_disable(struct brw_context *brw, */ static void gen6_blorp_emit_clear_params(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 | @@ -910,7 +910,7 @@ gen6_blorp_emit_clear_params(struct brw_context *brw, /* 3DSTATE_DRAWING_RECTANGLE */ void gen6_blorp_emit_drawing_rectangle(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2)); @@ -924,7 +924,7 @@ gen6_blorp_emit_drawing_rectangle(struct brw_context *brw, /* 3DSTATE_VIEWPORT_STATE_POINTERS */ void gen6_blorp_emit_viewport_state(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { struct brw_cc_viewport *ccv; uint32_t cc_vp_offset; @@ -949,7 +949,7 @@ gen6_blorp_emit_viewport_state(struct brw_context *brw, /* 3DPRIMITIVE */ static void gen6_blorp_emit_primitive(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { BEGIN_BATCH(6); OUT_BATCH(CMD_3D_PRIM << 16 | (6 - 2) | @@ -974,7 +974,7 @@ gen6_blorp_emit_primitive(struct brw_context *brw, */ void gen6_blorp_exec(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { uint32_t cc_blend_state_offset = 0; uint32_t cc_state_offset = 0; diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index 568a22f2c42..f2ed4736856 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp @@ -407,7 +407,7 @@ gen7_blorp_emit_streamout_disable(struct brw_context *brw) static void gen7_blorp_emit_sf_config(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { /* 3DSTATE_SF * @@ -461,7 +461,7 @@ gen7_blorp_emit_sf_config(struct brw_context *brw, */ static void gen7_blorp_emit_wm_config(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { const struct brw_blorp_prog_data *prog_data = params->wm_prog_data; uint32_t dw1 = 0, dw2 = 0; @@ -523,7 +523,7 @@ gen7_blorp_emit_wm_config(struct brw_context *brw, */ static void gen7_blorp_emit_ps_config(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { const struct brw_blorp_prog_data *prog_data = params->wm_prog_data; uint32_t dw2, dw4, dw5; @@ -631,7 +631,7 @@ gen7_blorp_emit_constant_ps_disable(struct brw_context *brw) static void gen7_blorp_emit_depth_stencil_config(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { const uint8_t mocs = GEN7_MOCS_L3; uint32_t surfwidth, surfheight; @@ -766,7 +766,7 @@ gen7_blorp_emit_depth_disable(struct brw_context *brw) */ void gen7_blorp_emit_clear_params(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { BEGIN_BATCH(3); OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2)); @@ -779,7 +779,7 @@ gen7_blorp_emit_clear_params(struct brw_context *brw, /* 3DPRIMITIVE */ void gen7_blorp_emit_primitive(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { BEGIN_BATCH(7); OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2)); @@ -799,7 +799,7 @@ gen7_blorp_emit_primitive(struct brw_context *brw, */ void gen7_blorp_exec(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { if (brw->gen >= 8) return; diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.cpp b/src/mesa/drivers/dri/i965/gen8_blorp.cpp index 4bb43be00d7..d02a003abf5 100644 --- a/src/mesa/drivers/dri/i965/gen8_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen8_blorp.cpp @@ -126,7 +126,7 @@ gen8_blorp_emit_surface_state(struct brw_context *brw, static uint32_t gen8_blorp_emit_blend_state(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { uint32_t blend_state_offset; @@ -292,7 +292,7 @@ gen8_blorp_emit_raster_state(struct brw_context *brw) static void gen8_blorp_emit_sbe_state(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { /* 3DSTATE_SBE */ { @@ -369,7 +369,7 @@ gen8_blorp_emit_wm_state(struct brw_context *brw) */ static void gen8_blorp_emit_ps_config(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { const struct brw_blorp_prog_data *prog_data = params->wm_prog_data; uint32_t dw3, dw5, dw6, dw7; @@ -429,7 +429,7 @@ gen8_blorp_emit_ps_blend(struct brw_context *brw) static void gen8_blorp_emit_ps_extra(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { const struct brw_blorp_prog_data *prog_data = params->wm_prog_data; uint32_t dw1 = 0; @@ -530,7 +530,7 @@ gen8_blorp_emit_vf_state(struct brw_context *brw) static void gen8_blorp_emit_depth_stencil_state(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { const unsigned pkt_len = brw->gen >= 9 ? 4 : 3; @@ -585,7 +585,7 @@ gen8_blorp_emit_constant_ps(struct brw_context *brw, static uint32_t gen8_blorp_emit_surface_states(struct brw_context *brw, - const brw_blorp_params *params) + const struct brw_blorp_params *params) { uint32_t wm_surf_offset_renderbuffer; uint32_t wm_surf_offset_texture = 0; @@ -628,7 +628,7 @@ gen8_blorp_emit_surface_states(struct brw_context *brw, * \copydoc gen6_blorp_exec() */ void -gen8_blorp_exec(struct brw_context *brw, const brw_blorp_params *params) +gen8_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params) { uint32_t wm_bind_bo_offset = 0; -- 2.30.2