From b3f960751234b26224a9e7f22f05ee73b83e2ca5 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 11 May 2017 11:50:07 -0700 Subject: [PATCH] xilinx mig: put a buffer infront of the controller (#13) This makes placement of the L2 and DDR controller easier. --- src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala index c248f6c..58d14f4 100644 --- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala +++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala @@ -36,10 +36,12 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC val indexer = LazyModule(new AXI4IdIndexer(idBits = 4)) val deint = LazyModule(new AXI4Deinterleaver(p(coreplex.CacheBlockBytes))) val yank = LazyModule(new AXI4UserYanker) + val buffer = LazyModule(new AXI4Buffer) xing.node := node val monitor = (toaxi4.node := xing.node) - axi4 := yank.node + axi4 := buffer.node + buffer.node := yank.node yank.node := deint.node deint.node := indexer.node indexer.node := toaxi4.node @@ -85,7 +87,7 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC xing.module.io.in_reset := reset xing.module.io.out_clock := blackbox.io.ui_clk xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst - (Seq(toaxi4, indexer, deint, yank) ++ monitor) foreach { lm => + (Seq(toaxi4, indexer, deint, yank, buffer) ++ monitor) foreach { lm => lm.module.clock := blackbox.io.ui_clk lm.module.reset := blackbox.io.ui_clk_sync_rst } -- 2.30.2