From b3f9aa11be87877a278f2233aa25dcfdc3c9b466 Mon Sep 17 00:00:00 2001 From: bunnie Date: Fri, 24 Jan 2020 14:58:51 +0800 Subject: [PATCH] add option for BUFGCE to the clock generator buffer types --- litex/soc/cores/clock.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py index a36f9a2f..3d427bcf 100644 --- a/litex/soc/cores/clock.py +++ b/litex/soc/cores/clock.py @@ -41,7 +41,7 @@ class XilinxClocking(Module, AutoCSR): raise ValueError self.clkin_freq = freq - def create_clkout(self, cd, freq, phase=0, buf="bufg", margin=1e-2, with_reset=True): + def create_clkout(self, cd, freq, phase=0, buf="bufg", margin=1e-2, with_reset=True, clk_ce=None): assert self.nclkouts < self.nclkouts_max clkout = Signal() self.clkouts[self.nclkouts] = (clkout, freq, phase, margin) @@ -57,6 +57,8 @@ class XilinxClocking(Module, AutoCSR): self.specials += Instance("BUFG", i_I=clkout, o_O=clkout_buf) elif buf == "bufr": self.specials += Instance("BUFR", i_I=clkout, o_O=clkout_buf) + elif buf == "bufgce" and clk_ce != None: + self.specials += Instance("BUFGCE", i_I=clkout, o_O=clkout_buf, i_CE=clk_ce) else: raise ValueError -- 2.30.2