From b3faf5f0da631575917c5e27a88256a2cc1c7cb0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 26 Feb 2015 12:10:41 +0100 Subject: [PATCH] mibuild: better file organization (create directory for each vendor and move programmers in it) --- examples/cordic/cordic_impl.py | 2 +- mibuild/altera/__init__.py | 0 mibuild/altera/programmer.py | 10 ++++++ .../{altera_quartus.py => altera/quartus.py} | 0 mibuild/generic_programmer.py | 30 ++++++++++++++++ mibuild/platforms/apf27.py | 2 +- mibuild/platforms/apf51.py | 2 +- mibuild/platforms/de0nano.py | 4 +-- mibuild/platforms/kc705.py | 6 ++-- mibuild/platforms/lx9_microboard.py | 2 +- mibuild/platforms/m1.py | 4 +-- mibuild/platforms/mixxeo.py | 4 +-- mibuild/platforms/ml605.py | 2 +- mibuild/platforms/papilio_pro.py | 4 +-- mibuild/platforms/rhino.py | 2 +- mibuild/platforms/roach.py | 2 +- mibuild/platforms/usrp_b100.py | 2 +- mibuild/platforms/zedboard.py | 2 +- mibuild/platforms/ztex_115d.py | 2 +- mibuild/xilinx/__init__.py | 0 .../{xilinx_common.py => xilinx/common.py} | 0 mibuild/{xilinx_ise.py => xilinx/ise.py} | 7 ++-- mibuild/{ => xilinx}/programmer.py | 34 ++----------------- .../{xilinx_vivado.py => xilinx/vivado.py} | 9 ++--- 24 files changed, 73 insertions(+), 59 deletions(-) create mode 100644 mibuild/altera/__init__.py create mode 100644 mibuild/altera/programmer.py rename mibuild/{altera_quartus.py => altera/quartus.py} (100%) create mode 100644 mibuild/generic_programmer.py create mode 100644 mibuild/xilinx/__init__.py rename mibuild/{xilinx_common.py => xilinx/common.py} (100%) rename mibuild/{xilinx_ise.py => xilinx/ise.py} (97%) rename mibuild/{ => xilinx}/programmer.py (52%) rename mibuild/{xilinx_vivado.py => xilinx/vivado.py} (95%) diff --git a/examples/cordic/cordic_impl.py b/examples/cordic/cordic_impl.py index d4c2e066..a1f329b5 100644 --- a/examples/cordic/cordic_impl.py +++ b/examples/cordic/cordic_impl.py @@ -6,7 +6,7 @@ from migen.genlib.cordic import Cordic from mibuild.tools import mkdir_noerror from mibuild.generic_platform import * from mibuild.crg import SimpleCRG -from mibuild.xilinx_ise import XilinxISEPlatform +from mibuild.xilinx.ise import XilinxISEPlatform class CordicImpl(Module): def __init__(self, name, **kwargs): diff --git a/mibuild/altera/__init__.py b/mibuild/altera/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/mibuild/altera/programmer.py b/mibuild/altera/programmer.py new file mode 100644 index 00000000..c6f25cbe --- /dev/null +++ b/mibuild/altera/programmer.py @@ -0,0 +1,10 @@ +import subprocess + +from mibuild.generic_programmer import GenericProgrammer + +class USBBlaster(GenericProgrammer): + needs_bitreverse = False + + def load_bitstream(self, bitstream_file, port=0): + usb_port = "[USB-"+str(port)+"]" + subprocess.call(["quartus_pgm", "-m", "jtag", "-c", "USB-Blaster"+usb_port, "-o", "p;"+bitstream_file]) diff --git a/mibuild/altera_quartus.py b/mibuild/altera/quartus.py similarity index 100% rename from mibuild/altera_quartus.py rename to mibuild/altera/quartus.py diff --git a/mibuild/generic_programmer.py b/mibuild/generic_programmer.py new file mode 100644 index 00000000..da3b0c26 --- /dev/null +++ b/mibuild/generic_programmer.py @@ -0,0 +1,30 @@ +import os + +class GenericProgrammer: + def __init__(self, flash_proxy_basename=None): + self.flash_proxy_basename = flash_proxy_basename + self.flash_proxy_dirs = [ + "~/.migen", "/usr/local/share/migen", "/usr/share/migen", + "~/.mlabs", "/usr/local/share/mlabs", "/usr/share/mlabs"] + + def set_flash_proxy_dir(self, flash_proxy_dir): + if flash_proxy_dir is not None: + self.flash_proxy_dirs = [flash_proxy_dir] + + def find_flash_proxy(self): + for d in self.flash_proxy_dirs: + fulldir = os.path.abspath(os.path.expanduser(d)) + fullname = os.path.join(fulldir, self.flash_proxy_basename) + if os.path.exists(fullname): + return fullname + raise OSError("Failed to find flash proxy bitstream") + + # must be overloaded by specific programmer + def load_bitstream(self, bitstream_file): + raise NotImplementedError + + # must be overloaded by specific programmer + def flash(self, address, data_file): + raise NotImplementedError + + diff --git a/mibuild/platforms/apf27.py b/mibuild/platforms/apf27.py index 23c99cdd..048b857b 100644 --- a/mibuild/platforms/apf27.py +++ b/mibuild/platforms/apf27.py @@ -1,6 +1,6 @@ from mibuild.generic_platform import * from mibuild.crg import SimpleCRG -from mibuild.xilinx_ise import XilinxISEPlatform +from mibuild.xilinx.ise import XilinxISEPlatform _ios = [ ("clk0", 0, Pins("N9"), IOStandard("LVCMOS18")), diff --git a/mibuild/platforms/apf51.py b/mibuild/platforms/apf51.py index 78c8dc1f..e15eb27a 100644 --- a/mibuild/platforms/apf51.py +++ b/mibuild/platforms/apf51.py @@ -1,6 +1,6 @@ from mibuild.generic_platform import * from mibuild.crg import SimpleCRG -from mibuild.xilinx_ise import XilinxISEPlatform +from mibuild.xilinx.ise import XilinxISEPlatform _ios = [ ("clk3", 0, Pins("N8"), IOStandard("LVCMOS33")), diff --git a/mibuild/platforms/de0nano.py b/mibuild/platforms/de0nano.py index 0d567c15..d0c99046 100644 --- a/mibuild/platforms/de0nano.py +++ b/mibuild/platforms/de0nano.py @@ -3,8 +3,8 @@ from mibuild.generic_platform import * from mibuild.crg import SimpleCRG -from mibuild.altera_quartus import AlteraQuartusPlatform -from mibuild.programmer import USBBlaster +from mibuild.altera.quartus import AlteraQuartusPlatform +from mibuild.altera.programmer import USBBlaster _io = [ ("clk50", 0, Pins("R8"), IOStandard("3.3-V LVTTL")), diff --git a/mibuild/platforms/kc705.py b/mibuild/platforms/kc705.py index 468fc1dd..1deab34a 100644 --- a/mibuild/platforms/kc705.py +++ b/mibuild/platforms/kc705.py @@ -1,9 +1,9 @@ from mibuild.generic_platform import * from mibuild.crg import SimpleCRG from mibuild.xilinx_common import CRG_DS -from mibuild.xilinx_ise import XilinxISEPlatform -from mibuild.xilinx_vivado import XilinxVivadoPlatform -from mibuild.programmer import XC3SProg +from mibuild.xilinx.ise import XilinxISEPlatform +from mibuild.xilinx.vivado import XilinxVivadoPlatform +from mibuild.xilinx.programmer import XC3SProg _io = [ ("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")), diff --git a/mibuild/platforms/lx9_microboard.py b/mibuild/platforms/lx9_microboard.py index 08d61249..a46d6319 100644 --- a/mibuild/platforms/lx9_microboard.py +++ b/mibuild/platforms/lx9_microboard.py @@ -1,6 +1,6 @@ from mibuild.generic_platform import * from mibuild.crg import SimpleCRG -from mibuild.xilinx_ise import XilinxISEPlatform +from mibuild.xilinx.ise import XilinxISEPlatform _io = [ ("user_btn", 0, Pins("V4"), IOStandard("LVCMOS33"), diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py index 6f1e3655..37b12cf0 100644 --- a/mibuild/platforms/m1.py +++ b/mibuild/platforms/m1.py @@ -1,7 +1,7 @@ from mibuild.generic_platform import * from mibuild.crg import SimpleCRG -from mibuild.xilinx_ise import XilinxISEPlatform -from mibuild.programmer import UrJTAG +from mibuild.xilinx.ise import XilinxISEPlatform +from mibuild.xilinx.programmer import UrJTAG _io = [ ("user_led", 0, Pins("B16"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")), diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py index 69ea30c0..d09f546a 100644 --- a/mibuild/platforms/mixxeo.py +++ b/mibuild/platforms/mixxeo.py @@ -1,7 +1,7 @@ from mibuild.generic_platform import * from mibuild.crg import SimpleCRG -from mibuild.xilinx_ise import XilinxISEPlatform -from mibuild.programmer import UrJTAG +from mibuild.xilinx.ise import XilinxISEPlatform +from mibuild.xilinx.programmer import UrJTAG _io = [ ("user_led", 0, Pins("V5"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")), diff --git a/mibuild/platforms/ml605.py b/mibuild/platforms/ml605.py index ab263909..f8236800 100644 --- a/mibuild/platforms/ml605.py +++ b/mibuild/platforms/ml605.py @@ -1,6 +1,6 @@ from mibuild.generic_platform import * from mibuild.xilinx_common import CRG_DS -from mibuild.xilinx_ise import XilinxISEPlatform +from mibuild.xilinx.ise import XilinxISEPlatform _io = [ # System clock (Differential 200MHz) diff --git a/mibuild/platforms/papilio_pro.py b/mibuild/platforms/papilio_pro.py index 4e29ba5d..82315552 100644 --- a/mibuild/platforms/papilio_pro.py +++ b/mibuild/platforms/papilio_pro.py @@ -1,7 +1,7 @@ from mibuild.generic_platform import * from mibuild.crg import SimpleCRG -from mibuild.xilinx_ise import XilinxISEPlatform -from mibuild.programmer import XC3SProg +from mibuild.xilinx.ise import XilinxISEPlatform +from mibuild.xilinx.programmer import XC3SProg _io = [ ("user_led", 0, Pins("P112"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")), diff --git a/mibuild/platforms/rhino.py b/mibuild/platforms/rhino.py index 8aafa55d..f1af075e 100644 --- a/mibuild/platforms/rhino.py +++ b/mibuild/platforms/rhino.py @@ -1,6 +1,6 @@ from mibuild.generic_platform import * from mibuild.xilinx_common import CRG_DS -from mibuild.xilinx_ise import XilinxISEPlatform +from mibuild.xilinx.ise import XilinxISEPlatform _io = [ ("user_led", 0, Pins("Y3")), diff --git a/mibuild/platforms/roach.py b/mibuild/platforms/roach.py index 495b808f..d20d611b 100644 --- a/mibuild/platforms/roach.py +++ b/mibuild/platforms/roach.py @@ -1,5 +1,5 @@ from mibuild.generic_platform import * -from mibuild.xilinx_ise import XilinxISEPlatform +from mibuild.xilinx.ise import XilinxISEPlatform _io = [ ("epb", 0, diff --git a/mibuild/platforms/usrp_b100.py b/mibuild/platforms/usrp_b100.py index 9972d5b7..1fb30080 100644 --- a/mibuild/platforms/usrp_b100.py +++ b/mibuild/platforms/usrp_b100.py @@ -1,6 +1,6 @@ from mibuild.generic_platform import * from mibuild.xilinx_common import CRG_DS -from mibuild.xilinx_ise import XilinxISEPlatform +from mibuild.xilinx.ise import XilinxISEPlatform _io = [ ("clk64", 0, diff --git a/mibuild/platforms/zedboard.py b/mibuild/platforms/zedboard.py index 33c9fc16..2a3e91c6 100644 --- a/mibuild/platforms/zedboard.py +++ b/mibuild/platforms/zedboard.py @@ -1,6 +1,6 @@ from mibuild.generic_platform import * from mibuild.crg import SimpleCRG -from mibuild.xilinx_ise import XilinxISEPlatform +from mibuild.xilinx.ise import XilinxISEPlatform # Bank 34 and 35 voltage depend on J18 jumper setting _io = [ diff --git a/mibuild/platforms/ztex_115d.py b/mibuild/platforms/ztex_115d.py index ece202f6..970b1e7d 100644 --- a/mibuild/platforms/ztex_115d.py +++ b/mibuild/platforms/ztex_115d.py @@ -1,6 +1,6 @@ from mibuild.generic_platform import * from mibuild.crg import SimpleCRG -from mibuild.xilinx_ise import XilinxISEPlatform +from mibuild.xilinx.ise import XilinxISEPlatform _io = [ ("clk_fx", 0, Pins("L22"), IOStandard("LVCMOS33")), diff --git a/mibuild/xilinx/__init__.py b/mibuild/xilinx/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/mibuild/xilinx_common.py b/mibuild/xilinx/common.py similarity index 100% rename from mibuild/xilinx_common.py rename to mibuild/xilinx/common.py diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx/ise.py similarity index 97% rename from mibuild/xilinx_ise.py rename to mibuild/xilinx/ise.py index d291f72f..5935c1a0 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx/ise.py @@ -4,7 +4,8 @@ from migen.fhdl.std import * from migen.fhdl.structure import _Fragment from mibuild.generic_platform import * -from mibuild import tools, xilinx_common +from mibuild import tools +from mibuild.xilinx import common def _format_constraint(c): if isinstance(c, Pins): @@ -92,7 +93,7 @@ def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt, source = False build_script_contents = "# Autogenerated by mibuild\nset -e\n" if source: - settings = xilinx_common.settings(ise_path, ver, "ISE_DS") + settings = common.settings(ise_path, ver, "ISE_DS") build_script_contents += "source " + settings + "\n" if mode == "edif": ext = "edif" @@ -119,7 +120,7 @@ bitgen {bitgen_opt} {build_name}.ncd {build_name}.bit if r != 0: raise OSError("Subprocess failed") -class XilinxISEPlatform(xilinx_common.XilinxGenericPlatform): +class XilinxISEPlatform(common.XilinxGenericPlatform): xst_opt = """-ifmt MIXED -opt_mode SPEED -register_balancing yes""" diff --git a/mibuild/programmer.py b/mibuild/xilinx/programmer.py similarity index 52% rename from mibuild/programmer.py rename to mibuild/xilinx/programmer.py index 71a67281..79cf1557 100644 --- a/mibuild/programmer.py +++ b/mibuild/xilinx/programmer.py @@ -1,31 +1,13 @@ import subprocess -import os -class Programmer: - def __init__(self, flash_proxy_basename=None): - self.flash_proxy_basename = flash_proxy_basename - self.flash_proxy_dirs = [ - "~/.migen", "/usr/local/share/migen", "/usr/share/migen", - "~/.mlabs", "/usr/local/share/mlabs", "/usr/share/mlabs"] - - def set_flash_proxy_dir(self, flash_proxy_dir): - if flash_proxy_dir is not None: - self.flash_proxy_dirs = [flash_proxy_dir] - - def find_flash_proxy(self): - for d in self.flash_proxy_dirs: - fulldir = os.path.abspath(os.path.expanduser(d)) - fullname = os.path.join(fulldir, self.flash_proxy_basename) - if os.path.exists(fullname): - return fullname - raise OSError("Failed to find flash proxy bitstream") +from mibuild.generic_programmer import GenericProgrammer def _run_urjtag(cmds): with subprocess.Popen("jtag", stdin=subprocess.PIPE) as process: process.stdin.write(cmds.encode("ASCII")) process.communicate() -class UrJTAG(Programmer): +class UrJTAG(GenericProgrammer): needs_bitreverse = True def load_bitstream(self, bitstream_file): @@ -49,7 +31,7 @@ flashmem "{address}" "{data_file}" noverify """.format(flash_proxy=flash_proxy, address=address, data_file=data_file) _run_urjtag(cmds) -class XC3SProg(Programmer): +class XC3SProg(GenericProgrammer): needs_bitreverse = False def __init__(self, cable, flash_proxy_basename=None): @@ -62,13 +44,3 @@ class XC3SProg(Programmer): def flash(self, address, data_file): flash_proxy = self.find_flash_proxy() subprocess.call(["xc3sprog", "-v", "-c", self.cable, "-I"+flash_proxy, "{}:w:0x{:x}:BIN".format(data_file, address)]) - -class USBBlaster(Programmer): - needs_bitreverse = False - - def load_bitstream(self, bitstream_file, port=0): - usb_port = "[USB-"+str(port)+"]" - subprocess.call(["quartus_pgm", "-m", "jtag", "-c", "USB-Blaster"+usb_port, "-o", "p;"+bitstream_file]) - - def flash(self, address, data_file): - raise NotImplementedError diff --git a/mibuild/xilinx_vivado.py b/mibuild/xilinx/vivado.py similarity index 95% rename from mibuild/xilinx_vivado.py rename to mibuild/xilinx/vivado.py index d55c930e..49747179 100644 --- a/mibuild/xilinx_vivado.py +++ b/mibuild/xilinx/vivado.py @@ -7,7 +7,8 @@ from migen.fhdl.std import * from migen.fhdl.structure import _Fragment from mibuild.generic_platform import * -from mibuild import tools, xilinx_common +from mibuild import tools +from mibuild.xilinx import common def _format_constraint(c): if isinstance(c, Pins): @@ -78,7 +79,7 @@ def _run_vivado(build_name, vivado_path, source, ver=None): r = subprocess.call([build_script_file]) else: build_script_contents = "# Autogenerated by mibuild\nset -e\n" - settings = xilinx_common.settings(vivado_path, ver) + settings = common.settings(vivado_path, ver) build_script_contents += "source " + settings + "\n" build_script_contents += "vivado -mode batch -source " + build_name + ".tcl\n" build_script_file = "build_" + build_name + ".sh" @@ -88,9 +89,9 @@ def _run_vivado(build_name, vivado_path, source, ver=None): if r != 0: raise OSError("Subprocess failed") -class XilinxVivadoPlatform(xilinx_common.XilinxGenericPlatform): +class XilinxVivadoPlatform(common.XilinxGenericPlatform): def __init__(self, *args, **kwargs): - xilinx_common.XilinxGenericPlatform.__init__(self, *args, **kwargs) + common.XilinxGenericPlatform.__init__(self, *args, **kwargs) self.bitstream_commands = [] self.additional_commands = [] -- 2.30.2