From b425b57d1e215810ac1ddabba62e89c8bd39a453 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 10 Oct 2016 13:23:55 +0200 Subject: [PATCH] radeonsi: emit TA_CS_BC_BASE_ADDR on SI only if the kernel allows it MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Edmondo Tommasina Reviewed-by: Alex Deucher Reviewed-by: Edward O'Callaghan Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_compute.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index e59bafeb9b6..632839ff3a5 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -251,7 +251,12 @@ static void si_initialize_compute(struct si_context *sctx) radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */ radeon_emit(cs, bc_va >> 40); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */ } else { - radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8); + if (sctx->screen->b.info.drm_major == 3 || + (sctx->screen->b.info.drm_major == 2 && + sctx->screen->b.info.drm_minor >= 48)) { + radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, + bc_va >> 8); + } } sctx->cs_shader_state.emitted_program = NULL; -- 2.30.2