From b43488cc6057615ff5579d83181fa7e9ec225eaa Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sat, 20 Nov 2021 14:47:51 +0000
Subject: [PATCH]

---
 3d_gpu/architecture/regfile.mdwn | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn
index 3aa7ba12c..bc63a5728 100644
--- a/3d_gpu/architecture/regfile.mdwn
+++ b/3d_gpu/architecture/regfile.mdwn
@@ -22,7 +22,7 @@ For a GPU, the FP and Integer registers need to be a massive 128 x 64-bit.
 Video walkthrough of regfile relationship to Function Units in core:
 <https://youtu.be/7Th1b-jq40k>
 
-[[!img core_regfiles_fus_pickers.jpg size="500px"]]
+[[!img core_regfiles_fus_pickers.jpg size="700x"]]
 
 # Regfile groups, Port Allocations and bit-widths
 
@@ -103,7 +103,7 @@ Notes:
 
 Click on the image to expand it full-screen:
 
-[[!img regfile_hilo_32_odd_even.png size="500px"]]
+[[!img regfile_hilo_32_odd_even.png size="900x"]]
 
 # Regspecs
 
-- 
2.30.2