From b43495aab16e7d09f184214b896aad28c094d337 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 12 Sep 2015 16:39:39 +0800 Subject: [PATCH] build/xilinx: minor cleanup --- migen/build/xilinx/ise.py | 3 +-- migen/build/xilinx/platform.py | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/migen/build/xilinx/ise.py b/migen/build/xilinx/ise.py index 19896038..65126a10 100644 --- a/migen/build/xilinx/ise.py +++ b/migen/build/xilinx/ise.py @@ -4,7 +4,6 @@ import sys from migen.fhdl.std import * from migen.fhdl.structure import _Fragment - from migen.build.generic_platform import * from migen.build import tools from migen.build.xilinx import common @@ -134,7 +133,7 @@ def _default_ise_path(): def _default_source(): - return False if sys.platform == "win32" else True + return sys.platform != "win32" class XilinxISEToolchain: diff --git a/migen/build/xilinx/platform.py b/migen/build/xilinx/platform.py index c5422282..d4ca4b18 100644 --- a/migen/build/xilinx/platform.py +++ b/migen/build/xilinx/platform.py @@ -17,7 +17,7 @@ class XilinxPlatform(GenericPlatform): def get_verilog(self, *args, special_overrides=dict(), **kwargs): so = dict(common.xilinx_special_overrides) if self.device[:3] == "xc7": - so.update(dict(common.xilinx_s7_special_overrides)) + so.update(common.xilinx_s7_special_overrides) so.update(special_overrides) return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs) -- 2.30.2