From b4393a92148c85223bf571d7f77ab2807a50ee2e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 5 Jun 2020 04:53:52 +0100 Subject: [PATCH] refer to srr0/1 not a/b --- src/soc/fu/trap/main_stage.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index 67061cb4..964cd6b7 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -214,10 +214,10 @@ class TrapMainStage(PipeModBase): ctrl_tmp.msr(MSR_DR) <= '1'; end if; """ - comb += nia_o.data.eq(br_ext(a_i[2:])) + comb += nia_o.data.eq(br_ext(srr0_i[2:])) comb += nia_o.ok.eq(1) comb += msr_copy(msr_o.data, srr1_i, zero_me=False) # don't zero - with m.If(a[MSR_PR]): + with m.If(srr1_i[MSR_PR]): msr_o[MSR_EE].eq(1) msr_o[MSR_IR].eq(1) msr_o[MSR_DR].eq(1) -- 2.30.2