From b4562c8aa2a29589f28a5ecf63611aa1a9515d54 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 17 Jul 2020 13:13:51 +0100 Subject: [PATCH] whitespace --- libreriscv | 2 +- src/soc/fu/div/pipe_data.py | 12 ++++++++---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/libreriscv b/libreriscv index d83e5ccb..12e9237b 160000 --- a/libreriscv +++ b/libreriscv @@ -1 +1 @@ -Subproject commit d83e5ccbacd56e762bedc660cdd930264e12b81b +Subproject commit 12e9237b896ad233cb18946b34dab17d976f415c diff --git a/src/soc/fu/div/pipe_data.py b/src/soc/fu/div/pipe_data.py index 970ac7cf..b029f04b 100644 --- a/src/soc/fu/div/pipe_data.py +++ b/src/soc/fu/div/pipe_data.py @@ -54,7 +54,8 @@ class DivPipeKindConfig: class DivPipeKind(enum.Enum): # use ieee754.div_rem_sqrt_rsqrt.core.DivPipeCore* DivPipeCore = enum.auto() - # use nmigen's built-in div and rem operators -- only suitable for simulation + # use nmigen's built-in div and rem operators -- only suitable for + # simulation SimOnly = enum.auto() # use a FSM-based div core FSMCore = enum.auto() @@ -142,14 +143,17 @@ class CoreBaseData(DivInputData): class CoreInputData(CoreBaseData): def __init__(self, pspec): - super().__init__(pspec, pspec.div_pipe_kind.config.core_input_data_class) + super().__init__(pspec, + pspec.div_pipe_kind.config.core_input_data_class) class CoreInterstageData(CoreBaseData): def __init__(self, pspec): - super().__init__(pspec, pspec.div_pipe_kind.config.core_interstage_data_class) + super().__init__(pspec, + pspec.div_pipe_kind.config.core_interstage_data_class) class CoreOutputData(CoreBaseData): def __init__(self, pspec): - super().__init__(pspec, pspec.div_pipe_kind.config.core_output_data_class) + super().__init__(pspec, + pspec.div_pipe_kind.config.core_output_data_class) -- 2.30.2