From b467827f51016fa5c8c96faa25b4e0790197a9f7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 17 Mar 2021 22:33:15 +0000 Subject: [PATCH] correct comments --- src/soc/decoder/isa/test_caller_svp64_predication.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/decoder/isa/test_caller_svp64_predication.py b/src/soc/decoder/isa/test_caller_svp64_predication.py index afd50141..d962c0db 100644 --- a/src/soc/decoder/isa/test_caller_svp64_predication.py +++ b/src/soc/decoder/isa/test_caller_svp64_predication.py @@ -53,7 +53,7 @@ class DecoderTestCase(FHDLTestCase): # therefore the operation that's carried out is: # GPR(10) = extsb(GPR(5)) # - # this is a type of back-to-back VGATHER and VSCATTER but it applies + # this is a type of back-to-back VREDUCE and VEXPAND but it applies # to *operations*, not just MVs like in traditional Vector ISAs # ascii graphic: # -- 2.30.2