From b46dbaf9834ca677d0a17628f182ca126d970569 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Wed, 22 Jun 2022 11:23:01 +0100
Subject: [PATCH]

---
 openpower/sv/svp64.mdwn | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index ede107e25..d1c5d76a9 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -416,6 +416,8 @@ is based on whether the number of src operands is 2 or 3.  With only
 * `RM-2P-1S1D` Twin Predication (src=1, dest=1)
 * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
 * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
+* `RM-2P-1S1D-PU` Twin Predication (src=1, dest=1), Pack/Unpack, primarily
+  for mv and swizzle.
 
 ## RM-1P-3S1D
 
@@ -468,7 +470,7 @@ augmented to 7 bits in length.
 
 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
 
-## MVRM-2P-1S1D
+## RM-2P-1S1D-PU
 
 | Field Name | Field bits | Description                     |
 |------------|------------|----------------------------|
-- 
2.30.2