From b47d05e4157342942b6a1730b566e63cc3f2f114 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 21 Mar 2021 21:52:34 +0000 Subject: [PATCH] --- openpower/sv/setvl.mdwn | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn index aac1c47d7..cd6a10f68 100644 --- a/openpower/sv/setvl.mdwn +++ b/openpower/sv/setvl.mdwn @@ -39,13 +39,15 @@ Page Faults etc. aside this is *guaranteed* 100% without fail to perform 64 unit # Format -*(Allocation of opcode TBD pending OPF ISA WG approval)* +*(Allocation of opcode TBD pending OPF ISA WG approval)*, +using EXT22 temporarily and fitting into the +[[sv/bitmanip]] space Form: SVL-Form (see [[isatables/fields.text]]) -| 0.5|6.10|11.15|16..23 | 24.25 | 26...30 |31| name | -| -- | -- | --- | ------ | ------ | ------- |--| ------- | -|OPCD| RT | RA | SVi / | vs ms | XO[0:4] |Rc| setvl | +| 0.5|6.10|11.15|16..23 | 24.25 | 26.30 |31| name | +| -- | -- | --- | ------ | ------ | ----- |--| ------- | +|OPCD| RT | RA | SVi / | vs ms | 11110 |Rc| setvl | Note that the immediate (`SVi`) spans 7 bits (16 to 22), and that bit 23 is reserved and must be zero. Setting bit 23 to 1 causes an illegal exception. -- 2.30.2