From b49a0750196767b35399f7999b0a52b3c87318ea Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 22 Jul 2022 19:14:14 +0100 Subject: [PATCH] remove numbering from primer summary --- openpower/simple_v_spec.tex | 2 +- openpower/svp64-primer/acronyms.tex | 2 +- openpower/svp64-primer/summary.tex | 10 +++++----- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/openpower/simple_v_spec.tex b/openpower/simple_v_spec.tex index df481533b..e7360f504 100644 --- a/openpower/simple_v_spec.tex +++ b/openpower/simple_v_spec.tex @@ -168,8 +168,8 @@ at: \part{Scalable Vectors Primer} -\chapter{Executive Summary} \input{svp64-primer/acronyms} +\chapter*{Executive Summary} \include{svp64-primer/summary} \bibliography{svp64-primer/references} \bibliographystyle{ieeetr} diff --git a/openpower/svp64-primer/acronyms.tex b/openpower/svp64-primer/acronyms.tex index 99d848554..dffc2bb10 100644 --- a/openpower/svp64-primer/acronyms.tex +++ b/openpower/svp64-primer/acronyms.tex @@ -1,4 +1,4 @@ -\section{List of Acronyms} +\section*{List of Acronyms} \begin{acronym} \acro{ASIC}{Application Specific Integrated Circuit} \acro{AVX-512}{Intel Advanced Vector Extensions 512-bit} diff --git a/openpower/svp64-primer/summary.tex b/openpower/svp64-primer/summary.tex index 9523bfdf3..cea39b10e 100644 --- a/openpower/svp64-primer/summary.tex +++ b/openpower/svp64-primer/summary.tex @@ -1,4 +1,4 @@ -\section{Summary} +\section*{Summary} The proposed \acs{SV} is a Scalable Vector Specification for a hardware for-loop \textbf{that ONLY uses scalar instructions}. @@ -51,7 +51,7 @@ the Power ISA's Supercomputing pedigree. \pagebreak -\subsection{What is SIMD?} +\subsection*{What is SIMD?} \acs{SIMD} is a way of partitioning existing \acs{CPU} registers of 64-bit length into smaller 8-, 16-, 32-bit pieces. @@ -78,7 +78,7 @@ scalar-only instructions. \textit{As long as the data width fits the workload, everything is fine}. \par -\subsection{Shortfalls of SIMD} +\subsection*{Shortfalls of SIMD} SIMD registers are of a fixed length and thus to achieve greater performance, CPU architects typically increase the width of registers (to 128-, 256-, 512-bit etc) for more partitions.\par Additionally, @@ -103,7 +103,7 @@ the number of instructions increase: Multi-issue decoding \end{itemize} -\subsection{Scalable Vector Architectures} +\subsection*{Scalable Vector Architectures} An older alternative exists to utilise data parallelism - vector architectures. Vector CPUs collect operands from the main memory, and store them in large, sequential vector registers.\par @@ -159,7 +159,7 @@ how a Vector's elements are sequentially and linearly mapped onto the \pagebreak -\subsection{Simple Vectorisation} +\subsection*{Simple Vectorisation} \acs{SV} is a Scalable Vector ISA designed for hybrid workloads (CPU, GPU, VPU, 3D). Includes features normally found only on Cray-style Supercomputers (Cray-1, NEC SX-Aurora) and GPUs. Keeps to a strict uniform RISC paradigm, -- 2.30.2