From b49d42520dbba44d6fc5421b57ea1202ed47252d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 11 Sep 2022 01:40:56 +0100 Subject: [PATCH] add CR5Operand and CR3Operand to power_insns.py --- src/openpower/decoder/power_enums.py | 4 +- src/openpower/decoder/power_insn.py | 82 +++++++++++++++++++++++++++- 2 files changed, 82 insertions(+), 4 deletions(-) diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index daadc555..365ced69 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -393,11 +393,11 @@ class RegType(Enum): FRS = FPR FRT = FPR - CR_REG = 2 + CR_REG = 2 # actually CR Field. the CR register is 32-bit. BF = CR_REG BFA = CR_REG - CR_BIT = 3 + CR_BIT = 3 # refers to one bit of the 32-bit CR register BA = CR_BIT BB = CR_BIT BC = CR_BIT diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index 5a1bcc1a..63db6856 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -651,11 +651,16 @@ class GPRFPROperand(RegisterOperand): bits = (len(span) + len(spec_span)) value = _SelectableInt(value=value.value, bits=bits) spec = _SelectableInt(value=spec.value, bits=bits) + # this is silly these should be in a general base class, + # settable by constructor + vshift = 2 + sshift = 5 + spshft = 0 if vector: - value = ((value << 2) | spec) + value = ((value << vshift) | (spec<>2, bits=bits) + spec = _SelectableInt(value=spec.value, bits=bits) + #print ("spec", bin(spec.value), spec.bits) + #print ("value", bin(value.value), value.bits) + #print ("lsbs", bin(lsbs.value), lsbs.bits) + # this is silly these should be in a general base class, + # settable by constructor + vshift = 4 + sshift = 3 + spshft = 2 + if vector: + value = ((value << vshift) | (spec<